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EM MICROELECTRONIC - MARIN SA
EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x
Sub-1V (0.6V) 8bit Flash MCU DC-DC Converter, E2PROM
Description
The EM6819 is designed to be battery operated for extended lifetime applications. Its large voltage range from 3.6V down to 0.9V makes it a perfect match for today's demanding applications. Brownout and powercheck functions ensure reliable operation at or near undervoltage conditions, offering greater reliability in complex operation modes. Each of the 24 I/Os are freely programmable and the microcontroller has a dual quartz and trimmable RC oscillator up to 15MHz. It has an 8-bit RISC architecture specially designed for very low power consumption. With 2 clocks per instruction, the EM6819 executes up to 7.5 MIPS at 15MHz and achieves astonishing 4000 MIPS/Watt.
Architecture
Features
Wide supply voltage range 0.9 V - 3.6 V Runs down to 0.6V with enabled DCDC and still 10mA load current True low current: typ 140uA at 3V, 1 MIPS Up to 7.5 MIPS at 15MHz DC-DC converter using just external coil and capacitor On-chip brownout detection PowerCheck functions at start-up 32 Voltage Level Detection on Supply or Input pin 3 terminal Operational Amplifier / Comparator ADC 10-bit, 8 channel Temperature sensor Voltage reference input/output Fast wake-up Up to 24 fully configurable I/Os Flash read monitoring system lowest voltages Dual clock mode, quartz and RC oscillators: o 2 MHz - 15MHz RC, pre-trimmed o Low freq RC Oscillator (8kHz) o 32768 Hz Xtal, 4MHz Resonator/Xtal, Ext Clock 8-bit CoolRISC architecture o 16 registers o 8*8bit hardware multiplier Power-On-Reset and watchdog GPNVM Memory o Sharing Instruction code and data Fully static 512 Byte RAM Internal and external interrupts Frequency generator 4 independent PWM outputs 8/16-bit timers Prescaler for RC and XTAL SPI interface Small size, Green mold / lead-free packages
Pinout for 32 lead QFN Others include SO8, TSSOP16/20/28, and QFN20/32
32 Lead QFN 5x5mm body
PB2 VSS 2 VSS VSS_ DC-DC
28 27 26 25
PB6
PB5
PB4
30
32
31
PB7 PA0 PC0 PA1 PC1 PA2 PC2 PA3
PB3
29
1 2 3 4 5 6 7 8
24 23 22
DCDC VSUP2 VSUP PB1 PB0 PC7 PA7 PA6
EM6819 DCDC
21 20 19 18 17
9
10
11
12
13
14
15
16
PC3
PA4
PC4
TM
PA5
PC5
Typical Applications
Metering Safety and Security devices Heat Cost Allocation Sensor Interfaces, Smoke detector Security Body care Sports Computer peripherals, Bluetooth chipset Wireless
Tools & Services
On chip debug system in the application ISP (In-system) programming C-compiler Windows-based software programs Programmer from different vendors Dedicated team of engineers for outstanding support
Copyright (c) 2010, EM Microelectronic-Marin SA 6819-DS, Version 3.0 ,8-Jul-10
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Power supply
Low power architecture Voltage regulator for internal logic supply External regulator capacitor Voltage mult: gives internal multiplied voltage to allow 0.9V start-up (Padring remains on VSUP) DC-DC Upconverter: with ext Coil and Cap. Increases the VSUP for the whole circuit I.e to 3V. Running down to 0.6V input voltage. 8-bit CoolRisc 816L Core 16 internal registers 4 hardware subroutine stacks 8-bit hardware multiplier 16.9k Byte shared Genaral Purpose Non Volatile Flash memory max 6k Instructions program memory max 12 kByte non volatile data memory 512 x 8-bit static SRAM 48 byte of Ram-cache for EEProm modification support Active mode: CPU and peripherals are running Standby mode: CPU halted, peripherals on Sleep mode: no clocks, data retained Power-Down mode, Reset state Wake Up Event from PortA inputs Power On Reset Reset from logic watchdog Brown out (as voltage supervisory function) Reset with Port A selection Flags to identify the reset source generation of watchdog reset after time out independent low frequency watchdog oscillator internal RC oscillator, 2MHz and 15MHz pre-trimmed internal 8 KHz RC Oscillator 32 KHz watch type Crystal or 4MHz Resonator/XTAL Two clock prescalers (dividers) for the peripheral clock generation: Prescaler 1 is a 15-stage divider Prescaler 2 is a 10-stage divider input clock software selectable fix intervall IRQ's external IRQ's from Port A, VLD, Comparator internal IRQ's from Timer, Prescaler, ADC, SPI Event from SPI/ADC and DoC
VLD
Detection of 32 voltage levels, internal reference Comparison against VSUP, input Pin or Op.Amp output 8-bit wide direct input read all functions bit-wise configurable Input , output Debouncer, IRQ on pos. or neg. edge Input combination reset Pullup, pulldown or nopull selectable Freq. Input for timer Analog In/Out 8 multipurpose I/O's 8-bit wide direct input read CMOS or Nch. Open Drain outputs all functions bit-wise configurable Input , output Pullup, pulldown or nopull selectable CMOS or Nch. Open Drain outputs 3 wire serial Interface, Sclk, Sin, Sout master and Slave mode Serial datastream output Event / IRQ Maped on port outputs 8 (16) bit wide, Zero Stop and Auto Reload mode External signal pulse width measurement PWM generation, IRQ Event Counter Input capture Output compare Automatically wakes up the circuit from sleep mode Enable/disable by register All 3 terminals mapped on PortA/PortC Output routed to VLD cell Amplifier or Comparator output Fully internal temperature sensor Multiplexed input to ADC On-chip Brown-Out detection, reset state Power check at Startup 10-bit, 8 channels ADC Single or Continuous mode External/internal reference voltage available on a pad Event / IRQ 2 wire serial interface debug and programming interface Flash programming Event / IRQ
Parallel In/Output Port A, Port C
CPU
-
Parallel In/Output Port B
-
Flash/EEPROM
RAM Operating modes
Serial Port Interface SPI
-
Timer (4 x 8-bit, or 2 x 16-bit)
Resets
Sleep Counter Wake-up (SCWUP) Op. Amplifier / Comparator
Watchdog timer Oscillator RC External Oscillator Prescaler's
Temp. Sensor Brown Out ADC
-
Interrupt
DoC (Debug on Chip)
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Pin Name PA0
Software selectable functions
Input with pullup/pulldown, IRQ capability, CPU read, wake-up, timer1 ext clock. Output of CPU write and a selection of internal clock and PWM signals. Analog input for ADC.
Remarks
PA1
Input with pullup/pulldown, IRQ capability, CPU read, wake-up, timer2 ext clock. Output of CPU write, selection of internal clock and PWM signals . Analog: input for ADC and VLD; Output for OPAMP.
PA2
Input with pullup/pulldown, IRQ capability, CPU read, wake-up, serial data input, timer3 ext clock. Output of CPU write, serial data out and selection of internal clock and PWM signals Analog: input for ADC,VLD and Opamp;
PA3
Input with pullup/pulldown, IRQ capability, CPU read, wake-up, serial data input, timer4 ext clock. Output of CPU write, serial data out and selection of internal clock and PWM signals Analog: input for ADC,VLD and Opamp;
PA4
Input with pullup/pulldown, IRQ capability, CPU read, wake-up, serial data. Output of CPU write and a selection of internal clock and PWM signals. Analog: XTAL/Resonator connection.
PA5 PA6
Input with pullup/pulldown, IRQ capability, CPU read, wake-up. Output of CPU write and a selection of internal clock and PWM signals. Input with pullup/pulldown, IRQ capability, CPU read, wake-up, serial clock.. Output of CPU write, serial clock and a selection of internal clock and PWM signals. Analog: input for VLD ; Output for VBGP
PA7
Input with pullup/pulldown, IRQ capability, CPU read, wake-up, serial clock.. Output of CPU write, serial data and a selection of internal clock and PWM signals. Analog: input for VLD ; Output for internal reference voltage
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
Input with pullup/pulldown, CPU read, serial data. Output of CPU write and a selection of internal clock and PWM signals. Input with pullup/pulldown, CPU read. Output of CPU write and a selection of internal clock and PWM signals. Input with pullup/pulldown, CPU read, serial clock. Output of CPU write, serial clock and a selection of internal clock and PWM signals. Input with pullup/pulldown, CPU read. Output of CPU write and a selection of internal clock and PWM signals. Input with pullup/pulldown, CPU read. Output of CPU write, serial data and a selection of internal clock and PWM signals. Input with pullup/pulldown, CPU read. Output of CPU write and a selection of internal clock and PWM signals. Input with pullup/pulldown, CPU read. Output of CPU write and a selection of internal clock and PWM signals. Input with pullup/pulldown, CPU read. Output of CPU write and a selection of internal clock and PWM signals. Input with pullup/pulldown, IRQ capability, CPU read, timer1 ext clock. GASP data GASP clock
PC0
Output of CPU write and a selection of internal clock and PWM signals. Analog input for ADC.
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PC1
Input with pullup/pulldown, IRQ capability, CPU read, timer2 ext clock. Output of CPU write, selection of internal clock and PWM signals . Analog: input for ADC and VLD; Output for OPAMP.
PC2
Input with pullup/pulldown, IRQ capability, CPU read. Output of CPU write, serial data, selection of internal clock and PWM signals . Analog: input for ADC and OPAMP.
PC3
Input with pullup/pulldown, IRQ capability, CPU read, timer4 ext clock. Output of CPU write, selection of internal clock and PWM signals . Analog: input for ADC and OPAMP.
PC4
Input with pullup/pulldown, IRQ capability, CPU read, external clock input Output of CPU write, selection of internal clock and PWM signals . Analog: XTAL/Resonator connection
PC5
Input with pullup/pulldown, IRQ capability, CPU read. Output of CPU write, selection of internal clock and PWM signals . Analog: input for VLD.
PC6
Input with pullup/pulldown, IRQ capability, CPU read, serial clock, timer1 ext clock Output of CPU write, serial clock, selection of internal clock and PWM signals . Analog: input for VLD.
PC7 TM VREG DC-DC VSUP VSUP2
Input with pullup/pulldown, IRQ capability, CPU read, timer3 ext clock Output of CPU write, selection of internal clock and PWM signals . GASP mode entry External Capacitance to maintain internal regulated voltage Coil connection in in case of DC-DC converter Main power supply pin. Connect to positive terminal of the DC-DC charge holder capacitance Supply filtering pin in case of DC-DC converter Connect to positive terminal of the DC-DC charge holder capacitance Connect to VSUP if DC-DC not used Only on DCDC Versions GASP mode
VSS VSS2
Main GND. This is also the circuit substrate potential. Connect to negative terminal of the DC-DC charge holder capacitance Ground noise filtering in case of DCDC converter used Connect to negative terminal of the DC-DC charge holder capacitance Connect to VSS if DC-DC not used Only on DCDC versions
VSS_ DC-DC
DCDC ground connection Connect to negative terminal of the DC-DC charge holder capacitance Connect to VSS if DC-DC not used
Only on DCDC versions
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TABLE OF CONTENTS 1. 2. EM6819 FAMILY SYSTEM OVERVIEW 11 12 13 13 13 13 14 14 15 16 17 18 18 18 18 19 20 27 28 29 30 31 31 32 32 32 33 33 33 33 34 34 35 35 35 36 37 37 38 39 39 39 40 40 41 42 43 43 43 43 43 43 43 44
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2.1 OPERATING MODES 2.1.1 Active mode 2.2 LOW POWER MODES 2.2.1 Standby mode 2.2.2 Sleep mode 2.2.3 Sleep Wake-up 2.2.4 Power-down mode 2.2.5 Operation mode registers 2.3 REGISTER TYPES 2.4 POWER MANAGEMENT 2.4.1 Brownout 2.4.2 Powercheck 2.4.3 POR 2.4.4 Powermanagment Registers 2.5 REGISTER MAP 2.6 PORT TERMINAL CONNECTION REFERENCE TABLE 2.7 TSSOP PACKAGE PINOUT CIRCUIT WITHOUT DC-DC AND S08 2.8 TSSOP PACKAGE PINOUT CIRCUIT WITH DC-DC 2.9 QFN PACKAGES WITH AND WITHOUT DCDC 3. CPU CORE CR816 3.1 PM_MISS FUNCTION (FLASH READ MONITOR) 4. NVM MEMORY 4.1 INTRODUCTION 4.2 NVM ARCHITECTURE 4.3 RAM CACHE 4.4 WRITE DATA IN NVM 4.4.1 Row and sector selection 4.4.2 Fast/slow operation 4.4.3 Erase 4.4.4 Write 4.5 ROW 61 SECTOR 5 4.6 ROW 62 SECTOR 5 4.6.1 Temperature tolerance 4.7 ROW 63 SECTOR 5 4.8 READ DATA IN NVM 4.9 ROW TO CACHE 4.9.1 NVM configuration registers 5. CRC CHECK 5.1 CRC CHECK ON PROGRAM AREA 5.2 CRC CHECK ON DATA AREA 6. ROM API ROUTINES 6.1 BOOT SEQUENCE 6.2 SUB-ROUTINES USED FOR APPLICATION 7. RAM 8. RESET CONTROLLER 8.1 RESET SOURCES 8.2 RESET SIGNALS 8.2.1 POR 8.2.2 PorLog 8.2.3 ResAna 8.2.4 ResSys 8.2.5 Reset Flags
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8.3 RESET REGISTERS OSCILLATOR AND CLOCKING STRUCTURE 44 45 46 46 47 47 48 48 49 50 52 54 54 55 55 56 56 56 56 57 57 57 58 59 59 59 60 60 60 63 63 63 64 65 65 65 66 66 67 67 68 68 69 69 69 71 72 72 72 72 72 72 73 75 75
9.
9.1 EXTERNAL CLOCK SELECTION 9.2 INTERNAL HIGH AND LOW FREQUENCY CLOCK SELECTION 9.2.1 external clock selection Restrictions 9.2.2 CPU Clock selection 9.2.3 Prescaler1 Clock selection 9.2.4 Prescaler 2 Clock selection 9.3 CLOCK CONTROL 9.4 OSCILLATORS CONTROL 9.5 CLOCK CONTROL REGISTERS 10. PRESCALER1 10.1 PRESCALER1 CLOCK SELECTION 10.2 PRESCALER1 RESET 10.3 PRESCALER REGISTERS 11. PRESCALER2 11.1 PRESCALER2 CLOCK SELECTION 11.2 PRESCALER2 RESET 11.3 PRESCALER2 REGISTERS 12. INTERRUPT AND EVENT CONTROLLER 12.1 INTERRUPTS GENERAL 12.1.1 Basic features 12.2 INTERRUPT ACQUISITION 12.3 INTERRUPTS FROM IO PORTS 12.4 INTERRUPT ACQUISITION MASKING. 12.4.1 Pre and Postmasking of interrupts 12.5 INTERRUPT ACQUISITION CLEARING 12.5.1 Software Interrupt acquisition set 12.6 INTERRUPT REGISTERS 12.7 EVENT GENERAL 12.7.1 Basic features 12.8 EVENT ACQUISITION 12.9 EVENT MASKING 12.10 EVENT ACQUISITION CLEARING 12.11 SOFTWARE EVENT SETTING 12.12 EVENT REGISTERS 13. CPU INTERRUPT AND EVENT HANDLING 13.1 INTERRUPT PRIORITY 13.2 CPU STATUS REGISTER 13.3 CPU STATUS REGISTER PIPELINE EXCEPTION 13.4 PROCESSOR VECTOR TABLE 13.5 CONTEXT SAVING 14. PORT A 14.1 PORT A TERMINAL MAPPING 14.2 PORT A IO OPERATION 14.3 OUTPUT SIGNALS ON PORT A 14.4 PORT A DEBOUNCER 14.5 PORT A INTERRUPT GENERATION 14.5.1 PA Irq in Active and Standby mode 14.5.2 PA Irq in Sleep Mode 14.6 PORT A RESET FUNCTION 14.7 PORT A WAKE-UP FUNCTION 14.8 PORT A REGISTERS 15. PORT B 15.1 PORT B TERMINAL MAPPING
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15.2 PORT B IO OPERATION 15.2.1 Gasp communication on PB7, PB6 15.3 OUTPUT SIGNALS ON PORT B 15.4 PORT B REGISTERS 16. PORT C 16.1 PORT C TERMINAL MAPPING 16.2 PORT C IO OPERATION 16.3 OUTPUT SIGNALS ON PORT C 16.4 PORT C DEBOUNCER 16.5 PORT C INTERRUPT GENERATION 16.5.1 PC Irq in Active and Standby mode 16.5.2 PC Irq in Sleep Mode 16.6 PORT C REGISTERS 17. TIMERS 17.1 TIMER CHAINING 17.2 TIMER CLOCK SOURCES 17.3 TIMER START 17.3.1 Software start - Stop 17.3.2 Hardware Start - Stop (period counting) 17.3.3 Hardware Start - Stop (puls counting) 17.4 AUTO-RELOAD MODE 17.5 AUTO-STOP MODE 17.6 TIMER INPUT CAPTURE 17.7 OUTPUT COMPARE 17.8 OUTPUT COMPARE - PWMX SIGNAL PORT MAPPING 17.9 TIMER INTERRUPTS 17.10 TIMER REGISTERS 18. SPI - SERIAL INTERFACE 18.1 SCLK - SPI MASTER/ SLAVE MODE AND CLOCK SELECTION 18.2 SIN PORT MAPPING 18.3 SOUT PORT MAPPING 18.4 SPI START - STOP 18.5 AUTO-START 18.6 RTZ POSITIVE EDGE TRANSMISSION 18.7 RTO POSITIVE EDGE TRANSMISSION 18.8 RTZ NEGATIVE EDGE TRANSMISSION 18.9 RTO NEGATIVE EDGE TRANSMISSION 18.10 SPI REGISTERS 19. WATCHDOG 19.1 WATCHDOG CLEAR 19.2 WATCHDOG DISABLING 19.3 WATCHDOG REGISTERS 20. SLEEP COUNTER WAKE-UP 20.1 SC WAKE-UP ENABLING 20.2 SC WAKE-UP DISABLING 20.3 SC WAKE-UP REGISTERS 21. 10-BITS ADC 21.1 CONDITIONER 21.1.1 Range selection 21.1.2 Reference selection 21.1.3 Analog input selection 21.2 ADC OFFSET TRIM SELECTION 21.2.1 Running mode 21.2.2 ADC enabling 21.2.3 ADC sampling rate 21.2.4 Low noise mode 75 76 77 78 79 79 79 81 82 82 82 82 83 85 85 86 87 87 87 88 89 89 90 92 93 94 94 98 99 100 100 100 100 101 101 101 102 102 103 103 103 104 105 105 106 106 107 107 107 108 109 109 110 110 111 111
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21.2.5 8bit ADC selection 21.3 ADC ACQUISITION SEQUENCE 21.4 ADC REGISTERS 22. TEMPERATURE SENSOR 22.1 TEMPERATURE SENSOR ENABLING 22.2 TEMPERATURE SENSOR REGISTERS 23. DC/DC CONVERTER 23.1 DC/DC ENABLING 23.2 DC/DC VOLTAGE SELECTION 23.3 DC/DC LOW NOISE MODE 23.4 DC-DC REGISTER 24. BAND GAP 24.1 BAND GAP REGISTER 25. VLD 25.1 VLD SOURCE AND LEVEL SELECTION 25.2 VLD ENABLE 25.3 VLD RESULT 25.4 VLD INTERRUPT 25.5 VLD TRIMMING 25.6 VLD REGISTERS 26. RC OSCILLATOR 26.1 RC OSCILLATORS REGISTERS 27. XTAL OSCILLATOR 32KHZ 28. RESONATOR 4MHZ 29. 8KHZ OSCILLATOR 30. ANALOG OPAMP 30.1 SELECT OPAMP/COMPARATOR 30.2 SUPPLY SELECTION 30.3 COMPARATOR RESULT 30.4 OPAMP REGISTERS 31. BLOCKS CONSUMPTION 32. TYPICAL T AND V DEPENDENCIES 32.1 IDD CURRENTS 32.1.1 General conditions 32.2 IOL AND IOH DRIVES 32.3 PULL-UP AND PULL-DOWN 32.4 RC OSCILLATOR 15MHZ AND 2MHZ 33. ELECTRICAL SPECIFICATION 33.1 33.2 33.3 33.4 33.5 33.6 33.7 33.8 33.9 33.10 33.11 33.12 33.13 33.14 33.15 ABSOLUTE MAXIMUM RATINGS HANDLING PROCEDURES STANDARD OPERATING CONDITIONS TYPICAL 32KHZ CRYSTAL SPECIFICATION TYPICAL 4MHZ CRYSTAL SPECIFICATION TYPICAL 4MHZ RESONATOR SPECIFICATION DC CHARACTERISTICS - POWER SUPPLY CURRENTS DC CHARACTERISTICS - VOLTAGE DETECTION LEVELS DC CHARACTERISTICS - REFERENCE VOLTAGE DC CHARACTERISTICS - DC-DC CONVERTER DC CHARACTERISTICS - OSCILLATORS DC CHARACTERISTICS - VHIGH DC CHARACTERISTICS - OPAMP DC CHARACTERISTICS - ADC DC CHARACTERISTICS - TEMPERATURE SENSOR
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111 112 112 113 113 113 114 114 114 114 115 116 116 117 117 117 117 118 118 118 119 119 120 121 122 123 123 123 124 124 125 126 126 126 133 136 138 139 139 139 139 140 140 140 141 143 143 144 144 145 145 145 146
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33.16 DC CHARACTERISTICS - I/O PINS 34. PACKAGE DRAWINGS 34.1 DIMENSIONS OF TSSOP28 PACKAGE 34.2 DIMENSIONS OF TSSOP24 PACKAGE 34.3 DIMENSIONS OF TSSOP20 PACKAGE 34.4 DIMENSIONS OF TSSOP16 PACKAGE 34.5 DIMENSIONS OF SO8 PACKAGE 34.6 DIMENSIONS OF QFN32 PACKAGE 34.7 DIMENSIONS OF QFN20 PACKAGE 35. PACKAGE MARKING 36. ERRATA 37. ORDERING INFORMATION 146 147 147 148 149 150 151 152 153 154 155 156
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Acronyms used in this document
MSB LSB CR / CPU/ NVM ROM RAM API GASP SW HW `1' / H / high `0' / L / low POR PWRC SCWUP VLD (T) (Q) (D) most significant bit least significant bit CoolRisc 816 CPU core Non Volatile Memory Read Only Memory Random Access Memory Application Program Interface General Access Serial Port Software Hardware Determines HIGH value, logical true Determines LOW value, logical false Power on reset Power check Sleep Counter Wake-up Voltage Level Detector Tested in the production Validated during qualification Guaranteed by the design
Nomenclature
Bit order scheme in this document is [n:0] where bit `n' is the MSB and bit `0' is the LSB, unless otherwise stated. Positive logic is assumed, High (`1') values means asserted or active state and Low (`0') value means not asserted or inactive state, unless otherwise stated. Register names and register bit names are written in bold typeface. Signal names are written in italic-bold type face. API subroutines are written in italic
Naming convention
The XTAL frequency is 32.768 kHz but is this document it is written 32 KHz (k=1000, K=1024).
Related Documents
[1] [2] CoolRISC 816L 8-bit Microprocessor Core, Hardware und Software Reference Manual V1.1 Mai 2002 ROM API document
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EM6819 family ensures 0.9V battery operations and much more ...
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EM6819 FAMILY
Part number
D
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2K word Flash (5.6kByte)
4K word Flash (11.5kByte)
6K word Flash (16.9kByte)
Copyright (c) 2010, EM Microelectronic-Marin SA 6819-DS, Version 3.0 ,8-Jul-10
12 to 20 08 to 12 12 to 24 12 to 24 12 to 24 4 4 4 4 PWM ADC OPAMP PwrCk VLD ISP SCWUP Pulse Width Modulation Analog to Digital Converter Operational Amplifier Power Check on start-up Voltage Level Detector In System Programming Sleep Counter Wake-Up 16 to 24 15MHz 15MHz 8 8 12 to 24 15MHz 4 4 8 15MHz 4 4 8 04 to 24 15MHz 4 4 8 16 to 24 15MHz 4 4 8 12 to 24 15MHz 4 4 8 12 to 24 15MHz 4 4 8 15MHz 4 4 8 15MHz 4 4 4 04 to 12 15MHz RC 8kHz 2MHz 15MHz 4 4 4 16 to 24 15MHz 15MHz 12 to 24 15MHz 04 to 12 15MHz SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C RC 8kHz 2MHz 15MHz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz
) el h nn to c og al ha r p c an so (u o s t C al en er p D S m on (u Ti p. tA iti M it m bi dd 8b A PW Te 10 PwrCk Brown-Out VLD 4 4 PwrCk Brown-Out OPAMP VLD 4 4 8 PwrCk Brown-Out OPAMP VLD 4 4 8 PwrCk Brown-Out OPAMP VLD 4 4 8 na tio di d A SCWUP WD SCWUP WD SCWUP WD SCWUP WD e ar S P I ftw / so hip C or f s) n e e( rit g O ag 1 w u ck te lf eb Pa No D se SO08 TSSOP16 TSSOP16-20-28 QFN20 TSSOP20-28 QFN20 TSSOP20-28 QFN20
EM6819F2-B006
2
4
256
0.9 - 3.6
EM6819F2-B000
2
4
512
0.9 - 3.6
EM6819F2-A000
2
4
512
0.9 - 3.6
EM6819F2-B300
2
4
512
1.8 - 5.5
EM6819F4-B005
4
8
256
0.9 - 3.6
EM6819F4-A005
4
8
256
0.9 - 3.6
EM6819F4-A000
4
8
512
0.9 - 3.6
EM6819F4-B000
4
8
512
0.9 - 3.6
11
SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C RC 8kHz 2MHz 15MHz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD
EM6819F4-B100
4
8
512
1.8 - 3.6
EM6819F4-B300
4
8
512
1.8 - 5.5
SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C SPI SW-UART / I2C RC 8kHz 2MHz 15MHz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz RC 8kHz 2MHz 15MHz Crystal 32kHz - 4Mhz
PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD PwrCk Brown-Out OPAMP VLD
SCWUP WD SCWUP WD SCWUP WD SCWUP WD SCWUP WD SCWUP WD
SO08 TSSOP16 TSSOP16-20 QFN20 TSSOP20-28 QFN20-32 TSSOP16-20-28 QFN20 TSSOP16-20-28 QFN20 TSSOP20-28 QFN20
EM6819F6-B004
6
12
512
0.9 - 3.6
EM6819F6-A000
6
12
512
0.9 - 3.6
EM6819F6-B100
6
12
512
1.8 - 3.6
EM6819F6-A100
6
12
512
1.8 - 3.6
EM6819F6-B300
6
8
512
1.8 - 5.5
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NVM RAM GPIO SPI RC Crystal WD
Non Volatile Memory Random Access Memory General Purpose Input Output Serial Peripheral Interface Fully embedded RC Oscillator Oscillator on chip Digital Watch-dog
SO08 TSSOP16-20-28 TSSOP20-28 QFN20-32 TSSOP16-20-28 QFN20 TSSOP20-28 QFN20-32 TSSOP16-20-28 QFN20 28.12.09 jag Note 1 : Ask for package & volume availability
SCWUP WD SCWUP WD SCWUP WD SCWUP WD SCWUP WD
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 2. SYSTEM OVERVIEW
The circuit's function blocks can be splitted in 5 different categories: Power management and security functions Memories and CPU Core Clock selection, clock switching and system peripherals Digital and Analog internal peripherals Communication interfaces via the IO pads Figure 1, EM6819 overview
Ldcdc DC-DC VREG
+
Cvreg
VSUP2 VSUP Cdcdc VSSDC VSS2 VSS
Power Supply 0.9 - 3.6V DC-DC Up-Converter 2.1V, 2.5V, 2.9V, 3.3V Voltage Regulator Power On Reset BrownOut & Power Check Watch Dog
Voltage Level Detector
32 - levels VSUP, PA, PC
POWER MANAGEMENT & SECURITY
GPNVM (FLASH) 16.9 kByte Data Memory Max 12 kB Instruction Memory Max 6 kInstr
RAM 512 Bytes
Fully static
ROM-API
Application subroutines
CoolRISC 8-bits
CR816L 16 registers HW multiplier
MEMORIES & CORE
Prescaler 1 Crystal 32kHz RC 8KHz
15 stages for RTC
X1(optional)
Crystal or Resonator
32kHz / 4MHz
4MHz
RC 2 MHz RC 15 MHz
Prescaler 2
10 stages
Sleep Counter wake-up
IRQ & Event controller
Reset & wake-up Controller
CLOCK & SYSTEM
Timer1, Timer2
2x8 bit or 16 bit PWM , Freq Gen Input capure Output compare
Timer3, Timer4
2x8 bit or 16 bit PWM , Freq Gen Input capure Output compare
SPI ADC 10 BIT
8 bits master or slave 8 channels
OPERTIONAL AMPLIFIER Temp Sensor
3 terminals, PA, PC
Digital & Analog PERIPHERALS
8 BITS PORT A
Pull-up, pull-down Interrupt, Capture Reset & Wake-up ADC, VLD, OPA,VREF Timer start & clock PWM, Signals
8 BITS PORT C 8 BITS PORT B
Pull-up, pull-down Interrupt,Capture ADC, VLD, OPA Timer start & clock PWM, Signals SPI or soft UART PWM, signals GASP interface
GASP Debug-on-Chip ISP Monitor 2 wire & TM IO's
PA[7:0]
PC[7:0]
PB[5:0]
PB[7:6]
TM
Power management and security functions The power managment block assures a proper system start at power up with Power on reset and power check function. The internal Brownout supervises the CPU and core internal power supply and asserts a reset at undervoltage. The watchdog function monitors the CPU execution, wheras the VLD can be used to monitor internal or external voltages. Its results are available to the user to take actions accordingly. The DC-DC upconverter can be switched on by demand. Memories and CPU Core This part contains all user program memory (FLASH), the non volatile data memory (mapped into the FLASH memory), the RAM and the vendor supplied application subroutines (ROM-API) for non volatile memory modifications. An essential part of this block is also the CR816 microprocessor core.
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Clock selection, clock switching and system pheripherals This block takes care of all internal and external clock sources. It synchronizes the clocks where needed and assures that the system can not hang-up due to faulty clock switching (i.e avoids switching to a non-present clock source). This block is also an essential part of the low power architecture by minimizing the total energy consumption by keeping the active clocking nodes to a strict minimum. Digital and Analog internal peripherals This part contains all the user peripherals such as timer, SPI, ADC, etc ... These peripherals are user configurable and fully adjustable to the user application. Communication interfaces via the IO pads Here are all the external communication channels grouped. All communication goes through at least 1 of the max 24 IO's. Several internal functions such as, serial interface, PWM, freq outputs, etc. are mapped to the IO's.
2.1 OPERATING MODES
The circuit has 4 distinctive operations modes wheras Standby, Sleep and Power-Down mode are specific low power modes Active CPU running all functions may be used StandBy CPU in Standby not clocked. Peripheral functions may be running Sleep CPU in Standby not clocked. Peripherals stopped except for specifically enabled functions Power-Down CPU and peripheral functions in reset. No Clocks. Pad configuration maintained.
2.1.1
ACTIVE MODE
The active mode is the default mode after any system reset. In this mode all peripherals are powered and ready to be used. All Low power modes are initiated from the active mode by executing the HALT instruction. If using an external high frequency clock input and the derived CPU clock is higher 6MHz the user shall set the bit FrcFastRead which acts as a booster for the Flash reading. For all internal clock selection the boosting is done automatically.
2.2 LOW POWER MODES
The Low power modes are enabled by the CPU HALT instruction execution. The resulting Low power mode selection then depends on the SelPwrDwn and SelSleep bit settings, both are located in the system register RegSysCfg1. Mode Active StandBy Sleep Power-Down HALT Instruction No Yes Yes Yes RegSysCfg1.SelSleep X 0 1 X RegSysCfg1.SelPwrDwn X 0 0 1
2.2.1
STANDBY MODE
This mode is activated by HALT instruction if SelPwrDwn='0' and SelSleep='0'. The active clock oscillator for the CPU clock source as selected by SelCkCR will be disabled in StandBy mode if it is not used by other block/peripheral or it's not forced-on. The Flash memory is disabled to save power. If fast wake-up is needed the user can choose to leave the Flash memory enabled in StandBy mode by setting the bit StdByFastWkUp in register RegSysCfg1 to `1'. Resume from standby mode and going back to active mode with an Event, an Interrupt or a system reset. Wake-up time from Standby mode is 1.5us if StdByFastWkUp ='1' and CPU is on 15 MHz with the 15 MHz RC oscillator forced on. Wake-up time from Standby mode is 10us if StdByFastWkUp ='1' and CPU is on 2 MHz with the 2 MHz RC oscillator forced on. Wake-up time from Standby mode is 150us if StdByFastWkUp ='0' and CPU is on 2 MHz with the 2 MHz RC oscillator forced on. Wake-up delay is measured from the time of the wake-up interrupt until the result of the first CPU instruction.
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The bit StdByFastWkUp ='1' will increase the standby power consumption by ~1.5uA at any CPU freq settings except if the CPU is set to RC_15MHz, RC_15MHz/2 or the bit FrcFastRead is set. In these cases the extra power consumption will be ~35uA. To avoid this extra 35uA of current the user must predivide the CPU clock just before going to standby mode to values below 6MHz by a) use RC_15MHz/4 or lower frequencies based on 2MHz, 32kHz, RC8k, b) or in case of external high freq clock input, set the CK_CPU predivider such that the resulting CPU frequeny is below 6MHz After wake-up the original high frequency CPU clock can immediately be reinstalled with little wake-up time penalty. Using StdByFastWkUp ='1' together with FrcFastRead='1' will draw additional 35uA independent of the selected CPU clock source. It should therefore be avoided by clearing FrcFastRead before going into standby mode.
2.2.2
SLEEP MODE
This mode is activated by HALT instruction if SelPwrDwn='0' and SelSleep='1'. In Sleep mode the Temperature sensor and the ADC are disabled. All oscillators are forced off except the RC 8kHz oscillator if used for sleep counter wake-up function. All register data are maintained during sleep. The Flash memory is switched off for power save. Resume from Sleep mode back to active mode with selected Interrupts and Events or by a system reset or by the sleep counter wakeup function SCWUP.
2.2.3
SLEEP WAKE-UP
Normal Wake-up from Sleep mode will take typically 250us until the 1st instruction after wake-up is executed. By setting the bit StdByFastWkUp prior to entering sleep mode the wake-up from sleep mode is greatly reduced. * In case of 2MHz RC Oscillator as CPU clock the wake-up time in fast mode is typically 18us * In case of 15MHz RC Oscillator as CPU clock the wake-up time in fast mode is typically 11us This wakeup time is measured from the wake-up event until the 3rd instruction after the wakeup event is changing a port output pin status. The bit StdByFastWkUp ='1' will increase the sleep power consumption by ~1.5uA at any CPU freq settings except if the CPU is set to RC_15MHz, RC_15MHz/2 or the bit FrcFastRead is set. In these cases the extra power consumption will be ~35uA. To avoid this extra 35uA of current the user must predivide the CPU clock just before going to sleep mode to values below 6MHz by c) use RC_15MHz/4 or lower frequencies based on 2MHz, 32kHz, RC8k, d) or in case of external high freq clock input, set the CK_CPU predivider such that the resulting CPU frequeny is below 6MHz After sleep wake-up the original high frequency CPU clock can immediately be reinstalled with almost no wake-up time penalty. Using StdByFastWkUp ='1' together with FrcFastRead='1' will draw additional 35uA independent of the selected CPU clock source. It should therefore be avoided by clearing FrcFastRead before going into sleep mode.
Note: DC/DC has to be switched off by the user before entering Sleep mode. Note: Interrupt sources for wake-up from the Sleep mode are defined in 12.2 Interrupt acquisition Note: Event sources for wake-up from the Sleep mode are defined in 12.8 Event acquisition
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2.2.4 POWER-DOWN MODE
This mode is activated by HALT instruction if SelPwrDwn='1'. All Clocks and oscillators including the RC 8 KHz are stopped. No circuit activity anymore. All register and RAM data are lost in Power-Down mode. The device is woken-up by a level change on PortA bits or by TM='1'; RegEnWkUpPA[n] will enable the related bit of PortA for this purpose when it is at high level. The wake-up from Power-Down acts as a reset, the CPU will start from scratch. The wake-up time from power down back to active mode is approximativly 6ms, and up to 10ms in low power mode. Note: Going into PowerDown mode without pad configuration latch shall be down in the following order: 1. Set the wake-up condition 2. Write the SelPwrDown bit 3. Execute HALT instruction 2.2.4.1 PAD CONFIGURATION LOCK IN POWER-DOWN If the bit LckPwrCfg in register RegResFlag is set, the configurations of all Ports bits (direction, pull-up, pull-down, qblock) are locked in the pad latches. As soon as the LckPwrCfg is set back to `0' the actual register configuration will be taken over. Note: To keep pad configuration in Power-Down mode, SW shall set LckPwrCfg to `1' just before going into Power-Down mode and sets it to `0' after wake-up from Power-Down mode. Note: Going into PowerDown mode without pad configuration latch shall be down in the following order: 1. Set the wake-up condition 2. Write the SelPwrDown bit 3. Write the LckPwrCfg bit 4. Execute HALT instruction Note: No data are kept in the registers and in the RAM in the Power-Down mode
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2.2.5 OPERATION MODE REGISTERS
RegSysCfg1 Type ResVal RW 0 RW 0 RW 1 RW '00' RW 0 RO 0 ResSrc ResSys ResSys ResAna ResSys ResSys System Configuration - 1 Description Select Sleep mode on Halt Select Power-Down mode on Halt Enable Brown Out Select Xtal Osc. ColdStart length Stand-by mode fast Wakeup VSUP is Low - Tripler activated
0x0000 Bits Name 7 SelSleep 6 SelPwrDwn 4 EnBrownOut 3:2 XtalCldStart 1 StdByFastWkUp 0 VSUPLow
0x0006 Bits Name 7 ResFlgPA 6 ResFlgWD 5 ResFlgBO 4 ResFlgGasp 3 ResFlgBE 0 LckPwrCfg
RegResFlg Type ResVal ResFlg 0 ResFlg 0 ResFlg 0 ResFlg 0 ResFlg 0 RW 0
ResSrc PorLog PorLog PorLog PorLog PorLog Por
Reset Flags Description Flag Reset from Port-A Flag Reset from WatchDog Flag Reset from Brown-Out Flag Reset from GASP Flag Reset from CoolRisc Bus-Error Lock configurations to be kept in Power-Down mode
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2.3 REGISTER TYPES
The peripheral registers are of different types. The specific type of the register is marked in its table definition. Used types are: RW, RO, OS, INT, INT-SET, STS, NI, RESFLG Read-Write Register (RW) - the software is able to write high and low values - the software is able to read out the last written value - the initial and reset value is according to its specified reset value Read Only register (RO) - the software is able to read out the current status of the hardware status - the initial and reset value is according to the value of the initial hardware status or hardware status after reset One Shot register (OS) - the software wriring of the specified value is producing the given action - the software always reads a low value Interrupt status register (INT) - Software writing `0' will clear a pending interrupt, clear has priority over a new arriving interrupt. - Software writing `1' will set the interrupt status bit (software interrupt). This has highest priority. - If the software reads the interrupt status at `1' it will clear it after the reading. - If the software reads `0', no action is performed. - An incoming hardware interrupt event will set the status bit, this action has priority over clear by software read. - The reset value is `0' Status register (STS) - the software can write only the allowed values into the register. These values are specified case-by-case. - the hardware may also be able to change the register value according to its function - the access priority software over hardware is specified case-by-case. - the readout value corresponds to the last change (software or hardware change) - the initial and reset value are specified case-by-case Not Implemented register (NI) - no action on write - the software is reading the specified constant value (normaly `0') Reset flag register (RESFLG) - an incoming hardware event sets or clears the register according on its specification - the readout value is according to the last hardware event and specified case-by-case. - The initial and reset value is according to the value specified case-by-case defined by its last hardware event - The software is able to clear the flag by writing `1' to it, writing `0' has no effect - Hardware event has priority over software access.
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2.4 POWER MANAGEMENT
The internal voltage regulator and the voltage multiplier assure a constant voltage VREG to the memory cells, GPNVM, RAM, ROM, the logic, the CPU core and sensible analog cells over the whole voltage range. For voltages below typ 2.2V the internal voltgage multiplier may become active and deliver the energy to sustain VREG voltage. While the internal voltage multiplier is enabled the maximum current draw of all VREG supplied peripherals is limited and the user shall not use operation frequencies above 2MHz nor switch on the 15Mhz RC oscillator. The flag VSUPLow shows the status of the voltage multiplier, if read `1' it means the multiplier is active and the current rescrictions apply.On low voltage supply status 1' the internal voltage multiplier maintains VREG voltage. Full frequency range can be used as long as VSUPLow = `0', the voltage multiplier is disabled and the logic regulator maintains VREG stable. Figure 2, Power Management architecture
2.4.1
BROWNOUT
If enabled, the BrownOut supervises the VREG voltage. As soon as Vreg drop below the minimal safe operation voltage for core operations and as such underpasses the brownout limits, reset ResBO is asserted. The circuit goes in reset state and can only recover from reset if the voltage rises above the PwrCheck level. (VPWRCheck > VBrwnout). The brownout can be disabled by EnBrownOut bit. The function is also automatically stopped in sleep mode if none of the Bandgap reference, ADC or OPAMP is active.
2.4.2
POWERCHECK
Powercheck is enabled on system power-up, it keeps the circuit in idle state until VREG voltage is sufficient high for safe core operation. ( VREG > VPWRCheck > VBrwnoutt) Powercheck is active after initial power-up, wake-up from Power-Down, wake-up from sleep after any system reset
2.4.3
POR
POR circuitry supervises the supply voltage VSUP at start-up and during all operation modes. As long as VSUP is below the VPOR voltage the circuit is in reset state. If the VSUP falls below VPOR the circuit will enter reset state even if brownout was disabled. At power-up the POR initializes the whole circuit except the RAM and powercheck is initiated.
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2.4.4 POWERMANAGMENT REGISTERS
RegSysCfg1 Type ResVal RW 0 RW 0 RW 1 RW '00' RW 0 RO 0 ResSrc ResSys ResSys ResAna ResSys ResSys System Configuration - 1 Description Select Sleep mode on Halt Select Power-Down mode on Halt Enable Brown Out Select Xtal Osc. ColdStart length fast Wakeup for Stand-by and Sleep mode VSUP is Low - Tripler activated
0x0000 Bits Name 7 SelSleep 6 SelPwrDwn 4 EnBrownOut 3:2 XtalCldStart 1 StdByFastWkUp 0 VSUPLow
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2.5 REGISTER MAP
Bit6
SelPwrDwn EnResPA(6) EnWkUpPA(6) SelCkExt(0) FrcEnRC2M SelCkPr1(1) ResFlgWD Presc1Len Presc1Val(6) Presc2Val(6) PADIn(6) PADOut(6) PAInpE(6) PAOE(6) PAPU(6) PAPD(6) PAOD(6) PA3OutSel(0) PA7OutSel(0) PA3DebSel(0) PA7DebSel(0) PA6DebSel(1) PA2DebSel(1) PA6OutSel(1) PA2OutSel(1) PAOD(5) PAOD(4) PA2OutSel(0) PA6OutSel(0) PA2DebSel(0) PA6DebSel(0) PAPD(5) PAPD(4) PAPU(5) PAPU(4) PAOE(5) PAOE(4) PAInpE(5) PAInpE(4) PADOut(5) PADOut(4) PADOut(3) PAInpE(3) PAOE(3) PAPU(3) PAPD(3) PAOD(3) PA1OutSel(1) PA5OutSel(1) PA1DebSel(1) PA5DebSel(1) PADIn(5) PADIn(4) PADIn(3) Presc2Val(5) Presc2Val(4) Presc2Val(3) Presc1Val(5) Presc1Val(4) Presc1Val(3) Presc1SelIntCk5/3 Presc2Clr Presc1Val(2) Presc2Val(2) PADIn(2) PADOut(2) PAInpE(2) PAOE(2) PAPU(2) PAPD(2) PAOD(2) PA1OutSel(0) PA5OutSel(0) PA1DebSel(0) PA5DebSel(0) ResFlgBO ResFlgGasp ResFlgBE SelCkPr1(0) SelCkPr2(2) SelCkPr2(1) SelCkPr2(0) FrcEnRC8k FrcEnExt SelCkCR(3) SelCkCR(2) SelCkHi(1) SelCkHi(0) SelCkLo(1) SelCkLo(0) EnWkUpPA(5) EnWkUpPA(4) EnWkUpPA(3) EnWkUpPA(2) EnResPA(5) EnResPA(4) EnResPA(3) EnResPA(2) EnBrownOut XtalCldStart(1) XtalCldStart(0) StdByFastWkUp EnResPA(1) EnWkUpPA(1) SelCkCR(1) Presc1Val(1) Presc2Val(1) PADIn(1) PADOut(1) PAInpE(1) PAOE(1) PAPU(1) PAPD(1) PAOD(1) PA0OutSel(1) PA4OutSel(1) PA0DebSel(1) PA4DebSel(1)
RegName
Address
Init.
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
VSUPLow EnResPA(0) EnWkUpPA(0) FrcFastRead SelCkCR(0) LckPwrCfg Presc1Val(0) Presc2Val(0) PADIn(0) PADOut(0) PAInpE(0) PAOE(0) PAPU(0) PAPD(0) PAOD(0) PA0OutSel(0) PA4OutSel(0) PA0DebSel(0) PA4DebSel(0)
RegSysCfg1
0x0000
0x10
SelSleep
RegEnResPA
0x0001
0x00
EnResPA(7)
RegEnWkUpPA
0x0002
0x00
EnWkUpPA(7)
RegClockCfg1
0x0003
0x18
SelCkExt(1)
RegClockCfg2
0x0004
0x03
FrcEnRC15M
RegClockCfg3
0x0005
0x70
SelCkPr1(2)
RegResFlg
0x0006
0x00
ResFlgPA
RegPrescCfg
0x0007
0x00
Presc1Clr
RegPresc1Val
0x0008
0xFF
Presc1Val(7)
RegPresc2Val
0x0009
0xFF
Presc2Val(7)
RegPADIn
0x000A
0x00
PADIn(7)
RegPADOut
0x000B
0x00
PADOut(7)
RegPAInpE
0x000C
0x00
PAInpE(7)
RegPAOE
0x000D
0x00
PAOE(7)
RegPAPU
0x000E
0x00
PAPU(7)
RegPAPD
0x000F
0x00
PAPD(7)
RegPAOD
0x0010
0x00
PAOD(7)
RegPAOutCfg0
0x0011
0x00
PA3OutSel(1)
RegPAOutCfg1
0x0012
0x00
PA7OutSel(1)
RegPADebCfg1
0x0013
0x00
PA3DebSel(1)
RegPADebCfg2
0x0014
0x00
PA7DebSel(1)
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Bit6
PAIntEdg(6) PBDIn(6) PBDOut(6) PBInpE(6) PBOE(6) PBPU(6) PBPD(6) PBOD(6) PB3OutSel(0) PB7OutSel(0) PCDIn(6) PCDOut(6) PCInpE(6) PCOE(6) PCPU(6) PCPD(6) PCOD(6) PC3OutSel(0) PC7OutSel(0) PC3DebSel(0) PC7DebSel(0) PCIntEdg(6) GaspDIn(6) GaspDOut(6) GaspDIn(5) GaspDOut(5) PCIntEdg(5) PC6DebSel(1) PC2DebSel(1) PC6OutSel(1) PC2OutSel(1) PC2OutSel(0) PC6OutSel(0) PC2DebSel(0) PC6DebSel(0) PCIntEdg(4) GaspDIn(4) GaspDOut(4) PCOD(5) PCOD(4) PCPD(5) PCPD(4) PCPU(5) PCPU(4) PCOE(5) PCOE(4) PCOE(3) PCPU(3) PCPD(3) PCOD(3) PC1OutSel(1) PC5OutSel(1) PC1DebSel(1) PC5DebSel(1) PCIntEdg(3) GaspDIn(3) GaspDOut(3) PCInpE(5) PCInpE(4) PCInpE(3) PCDOut(5) PCDOut(4) PCDOut(3) PCDIn(5) PCDIn(4) PCDIn(3) PB6OutSel(1) PB6OutSel(0) PB5OutSel(1) PB2OutSel(1) PB2OutSel(0) PB1OutSel(1) PBOD(5) PBOD(4) PBOD(3) PBOD(2) PB1OutSel(0) PB5OutSel(0) PCDIn(2) PCDOut(2) PCInpE(2) PCOE(2) PCPU(2) PCPD(2) PCOD(2) PC1OutSel(0) PC5OutSel(0) PC1DebSel(0) PC5DebSel(0) PCIntEdg(2) GaspDIn(2) GaspDOut(2) PBPD(5) PBPD(4) PBPD(3) PBPD(2) PBPU(5) PBPU(4) PBPU(3) PBPU(2) PBOE(5) PBOE(4) PBOE(3) PBOE(2) PBInpE(5) PBInpE(4) PBInpE(3) PBInpE(2) PBDOut(5) PBDOut(4) PBDOut(3) PBDOut(2) PBDOut(1) PBInpE(1) PBOE(1) PBPU(1) PBPD(1) PBOD(1) PB0OutSel(1) PB4OutSel(1) PCDIn(1) PCDOut(1) PCInpE(1) PCOE(1) PCPU(1) PCPD(1) PCOD(1) PC0OutSel(1) PC4OutSel(1) PC0DebSel(1) PC4DebSel(1) PCIntEdg(1) GaspDIn(1) GaspDOut(1) PBDIn(5) PBDIn(4) PBDIn(3) PBDIn(2) PBDIn(1) PAIntEdg(5) PAIntEdg(4) PAIntEdg(3) PAIntEdg(2) PAIntEdg(1)
RegName
Address
Init.
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PAIntEdg(0) PBDIn(0) PBDOut(0) PBInpE(0) PBOE(0) PBPU(0) PBPD(0) PBOD(0) PB0OutSel(0) PB4OutSel(0) PCDIn(0) PCDOut(0) PCInpE(0) PCOE(0) PCPU(0) PCPD(0) PCOD(0) PC0OutSel(0) PC4OutSel(0) PC0DebSel(0) PC4DebSel(0) PCIntEdg(0) GaspDIn(0) GaspDOut(0)
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RegPAIntEdg
0x0015
0xFF
PAIntEdg(7)
RegPBDIn
0x0016
0x00
PBDIn(7)
RegPBDOut
0x0017
0x00
PBDOut(7)
RegPBInpE
0x0018
0x00
PBInpE(7)
RegPBOE
0x0019
0x00
PBOE(7)
RegPBPU
0x001A
0x00
PBPU(7)
RegPBPD
0x001B
0x00
PBPD(7)
RegPBOD
0x001C
0x00
PBOD(7)
RegPBOutCfg0
0x001D
0x00
PB3OutSel(1)
RegPBOutCfg1
0x001E
0x00
PB7OutSel(1)
RegPCDIn
0x001F
0x00
PCDIn(7)
RegPCDOut
0x0020
0x00
PCDOut(7)
RegPCInpE
0x0021
0x00
PCInpE(7)
RegPCOE
0x0022
0x00
PCOE(7)
RegPCPU
0x0023
0x00
PCPU(7)
RegPCPD
0x0024
0x00
PCPD(7)
RegPCOD
0x0025
0x00
PCOD(7)
RegPCOutCfg0
0x0026
0x00
PC3OutSel(1)
RegPCOutCfg1
0x0027
0x00
PC7OutSel(1)
RegPCDebCfg1
0x0028
0x00
PC3DebSel(1)
RegPCDebCfg2
0x0029
0x00
PC7DebSel(1)
RegPCIntEdg
0x002A
0xFF
PCIntEdg(7)
RegGaspDIn
0x002B
0x00
GaspDIn(7)
RegGaspDOut
0x002C
0x00
GaspDOut(7)
Copyright (c) 2010, EM Microelectronic-Marin SA 6819-DS, Version 3.0 ,8-Jul-10
21
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R
EM6819FX-A00X, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x
Bit6
GaspMode DoCPM1L(6) DoCPM2L(6) DoCPM3L(6) DoCDM1L(6) DoCDM1M(6) DoCEnPM2 DoCPM2Stat CRC16DIn(6) CRC16L(6) CRC16M(6) Tim34Chain Tim1Pulse Tim1IntSel Tim1CptEdg(0) Tim1Status(6) Tim1Full(6) Tim1CmpVal(6) Tim1CptVal(6) Tim2IntSel Tim2CptEdg(0) Tim2SelStart(2) Tim2CptEvtSrc(1) Tim1CptVal(5) Tim1CmpVal(5) Tim1Full(5) Tim1Status(5) Tim1CptEvtSrc(1) Tim1CptEvtSrc(0) Tim1Status(4) Tim1Full(4) Tim1CmpVal(4) Tim1CptVal(4) Tim2SelStart(1) Tim2CptEvtSrc(0) Tim1SelStart(2) Tim1SelStart(1) Tim2SWStart Tim2Pulse Tim1AR Tim2AR CRC16M(5) CRC16M(4) CRC16L(5) CRC16L(4) CRC16L(3) CRC16M(3) Tim3AR Tim3SWStart Tim1SelStart(0) Tim1CmpFullAct(1) Tim1Status(3) Tim1Full(3) Tim1CmpVal(3) Tim1CptVal(3) Tim2SelStart(0) Tim2CmpFullAct(1) CRC16DIn(5) CRC16DIn(4) CRC16DIn(3) DoCPM3Stat DoCDM1Stat DoCEnPM3 DoCEnDM1(1) DoCEnDM1(0) DoCDM1M(5) DoCDM1M(4) DoCDM1M(3) DoCDM1L(5) DoCDM1L(4) DoCDM1L(3) DoCDM1L(2) DoCDM1M(2) CRC16DIn(2) CRC16L(2) CRC16M(2) Tim4AR Tim3Pulse Tim1SelClk(2) Tim1CmpFullAct(0) Tim1Status(2) Tim1Full(2) Tim1CmpVal(2) Tim1CptVal(2) Tim2SelClk(2) Tim2CmpFullAct(0) DoCPM3M(4) DoCPM3M(3) DoCPM3M(2) DoCPM3L(5) DoCPM3L(4) DoCPM3L(3) DoCPM3L(2) DoCPM2M(4) DoCPM2M(3) DoCPM2M(2) DoCPM2L(5) DoCPM2L(4) DoCPM2L(3) DoCPM2L(2) DoCPM1M(4) DoCPM1M(3) DoCPM1M(2) DoCPM1M(1) DoCPM2L(1) DoCPM2M(1) DoCPM3L(1) DoCPM3M(1) DoCDM1L(1) DoCDM1M(1) CRC16DIn(1) CRC16L(1) CRC16M(1) Tim1SWCpt Tim4SWStart Tim1SelClk(1) Tim1CmpValAct(1) Tim1Status(1) Tim1Full(1) Tim1CmpVal(1) Tim1CptVal(1) Tim2SelClk(1) Tim2CmpValAct(1) DoCPM1L(5) DoCPM1L(4) DoCPM1L(3) DoCPM1L(2) DoCPM1L(1) GaspSU GaspISP GaspDoC GaspTest -
RegName
Address
Init.
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DoCPM1L(0) DoCPM1M(0) DoCPM2L(0) DoCPM2M(0) DoCPM3L(0) DoCPM3M(0) DoCDM1L(0) DoCDM1M(0) CRC16DIn(0) CRC16L(0) CRC16M(0) Tim3SWCpt Tim4Pulse Tim1SelClk(0) Tim1CmpValAct(0) Tim1Status(0) Tim1Full(0) Tim1CmpVal(0) Tim1CptVal(0) Tim2SelClk(0) Tim2CmpValAct(0)
www..com
RegGaspMode
0x002D
0x00
GaspTM
RegDoCPM1L
0x002E
0x00
DoCPM1L(7)
RegDoCPM1M
0x002F
0x00
-
RegDoCPM2L
0x0030
0x00
DoCPM2L(7)
RegDoCPM2M
0x0031
0x00
-
RegDoCPM3L
0x0032
0x00
DoCPM3L(7)
RegDoCPM3M
0x0033
0x00
-
RegDoCDM1L
0x0034
0x00
DoCDM1L(7)
RegDoCDM1M
0x0035
0x00
DoCDM1M(7)
RegDoCEn
0x0036
0x00
DoCEnPM1
RegDoCStat
0x0037
0x00
DoCPM1Stat
RegCRC16DIn
0x0038
0x00
CRC16DIn(7)
RegCRC16L
0x0039
0x00
CRC16L(7)
RegCRC16M
0x003A
0x00
CRC16M(7)
RegTimersCfg
0x003B
0x00
Tim12Chain
RegTimersStart
0x003C
0x00
Tim1SWStart
RegTim1Cfg
0x003D
0x00
Tim1EnPWM
RegTim1CptCmpCfg
0x003E
0x00
Tim1CptEdg(1)
RegTim1Status
0x003F
0x00
Tim1Status(7)
RegTim1Full
0x0040
0xFF
Tim1Full(7)
RegTim1CmpVal
0x0041
0x00
Tim1CmpVal(7)
RegTim1CptVal
0x0042
0x00
Tim1CptVal(7)
RegTim2Cfg
0x0043
0x00
Tim2EnPWM
RegTim2CptCmpCfg
0x0044
0x00
Tim2CptEdg(1)
Copyright (c) 2010, EM Microelectronic-Marin SA 6819-DS, Version 3.0 ,8-Jul-10
22
www.emmicroelectronic.com
R
EM6819FX-A00X, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x
Bit6
Tim2Status(6) Tim2Full(6) Tim2CmpVal(6) Tim2CptVal(6) Tim3IntSel Tim3CptEdg(0) Tim3Status(6) Tim3Full(6) Tim3CmpVal(6) Tim3CptVal(6) Tim4IntSel Tim4CptEdg(0) Tim4Status(6) Tim4Full(6) Tim4CmpVal(6) Tim4CptVal(6) RunContMeas ADCSelRef(0) ADCOut0(6) ADCSelSrc(2) ADCOffsetL(6) EnComp OpAmpSelInpPos(0) OpAmpSup OpAmpSelInpNeg(1) ADCOffsetL(5) ADCSelSrc(1) ADCOut0(5) ADCSelRange(1) ADCSelRange(0) ADCOut0(4) ADCSelSrc(0) ADCOffsetL(4) CompRes OpAmpSelInpNeg(0) RunSinglMeas EnTempSens Tim4CptVal(5) Tim4CptVal(4) Tim4CmpVal(5) Tim4CmpVal(4) Tim4Full(5) Tim4Full(4) Tim4Status(5) Tim4Status(4) Tim4Status(3) Tim4Full(3) Tim4CmpVal(3) Tim4CptVal(3) ADCSmplRate(2) ADCLowNoise ADCOut0(3) StsTempSens ADCOffsetL(3) SelCompInt(1) OpAmpSelOut Tim4CptEvtSrc(1) Tim4CptEvtSrc(0) Tim4CmpFullAct(1) Tim4SelStart(2) Tim4SelStart(1) Tim4SelStart(0) Tim3CptVal(5) Tim3CptVal(4) Tim3CptVal(3) Tim3CmpVal(5) Tim3CmpVal(4) Tim3CmpVal(3) Tim3Full(5) Tim3Full(4) Tim3Full(3) Tim3Full(2) Tim3CmpVal(2) Tim3CptVal(2) Tim4SelClk(2) Tim4CmpFullAct(0) Tim4Status(2) Tim4Full(2) Tim4CmpVal(2) Tim4CptVal(2) ADCSmplRate(1) ADCOut0(2) ADCOutLSB ADCOffsetL(2) ADCOffsetM(2) SelCompInt(0) Tim3Status(5) Tim3Status(4) Tim3Status(3) Tim3Status(2) Tim3CptEvtSrc(1) Tim3CptEvtSrc(0) Tim3CmpFullAct(1) Tim3CmpFullAct(0) Tim3SelStart(2) Tim3SelStart(1) Tim3SelStart(0) Tim3SelClk(2) Tim2CptVal(5) Tim2CptVal(4) Tim2CptVal(3) Tim2CptVal(2) Tim2CmpVal(5) Tim2CmpVal(4) Tim2CmpVal(3) Tim2CmpVal(2) Tim2CmpVal(1) Tim2CptVal(1) Tim3SelClk(1) Tim3CmpValAct(1) Tim3Status(1) Tim3Full(1) Tim3CmpVal(1) Tim3CptVal(1) Tim4SelClk(1) Tim4CmpValAct(1) Tim4Status(1) Tim4Full(1) Tim4CmpVal(1) Tim4CptVal(1) ADCSmplRate(0) ADCOut0(1) ADCOut1(1) ADCOffsetL(1) ADCOffsetM(1) Tim2Full(5) Tim2Full(4) Tim2Full(3) Tim2Full(2) Tim2Full(1) Tim2Status(5) Tim2Status(4) Tim2Status(3) Tim2Status(2) Tim2Status(1)
RegName
Address
Init.
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Tim2Status(0) Tim2Full(0) Tim2CmpVal(0) Tim2CptVal(0) Tim3SelClk(0) Tim3CmpValAct(0) Tim3Status(0) Tim3Full(0) Tim3CmpVal(0) Tim3CptVal(0) Tim4SelClk(0) Tim4CmpValAct(0) Tim4Status(0) Tim4Full(0) Tim4CmpVal(0) Tim4CptVal(0) ADC8bit ADCOut0(0) ADCOut1(0) ADCOffsetL(0) ADCOffsetM(0) www..com
RegTim2Status
0x0045
0x00
Tim2Status(7)
RegTim2Full
0x0046
0xFF
Tim2Full(7)
RegTim2CmpVal
0x0047
0x00
Tim2CmpVal(7)
RegTim2CptVal
0x0048
0x00
Tim2CptVal(7)
RegTim3Cfg
0x0049
0x00
Tim3EnPWM
RegTim3CptCmpCfg
0x004A
0x00
Tim3CptEdg(1)
RegTim3Status
0x004B
0x00
Tim3Status(7)
RegTim3Full
0x004C
0xFF
Tim3Full(7)
RegTim3CmpVal
0x004D
0x00
Tim3CmpVal(7)
RegTim3CptVal
0x004E
0x00
Tim3CptVal(7)
RegTim4Cfg
0x004F
0x00
Tim4EnPWM
RegTim4CptCmpCfg
0x0050
0x00
Tim4CptEdg(1)
RegTim4Status
0x0051
0x00
Tim4Status(7)
RegTim4Full
0x0052
0xFF
Tim4Full(7)
RegTim4CmpVal
0x0053
0x00
Tim4CmpVal(7)
RegTim4CptVal
0x0054
0x00
Tim4CptVal(7)
RegADCCfg1
0x0055
0x00
EnADC
RegADCCfg2
0x0056
0x00
ADCSelRef(1)
RegADCOut0
0x0057
0x00
ADCOut0(7)
RegADCOut1
0x0058
0x00
ADCBusy
RegADCOffsetL
0x0059
0x00
ADCOffsetL(7)
RegADCOffsetM
0x005A
0x04
-
RegOpAmpCfg1
0x005B
0x00
EnOpAmp
RegOpAmpCfg2
0x005C
0x00
OpAmpSelInpPos(1)
Copyright (c) 2010, EM Microelectronic-Marin SA 6819-DS, Version 3.0 ,8-Jul-10
23
www.emmicroelectronic.com
R
EM6819FX-A00X, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x
Bit6
DC-DCLevel(1) VLDRes NVMEnWrite Int0StsTim1 Int1StsPort(1) Int2StsSlpCnt Int0MskTim1 Int1MskPort(1) Int2MskSlpCnt Int0PostMskTim1 Int1PostMskPort(1) Int2PostMskSlpCnt IntPortSrc(6) Evt1MskSC WDKey(6) WDLdValL(6) WDLdValM(6) WDStatL(6) WDStatM(6) SCStart SCLdVal0(6) SCLdVal0(5) WDStatM(5) WDStatL(5) WDLdValM(5) WDLdValL(5) WDKey(5) WDKey(4) WDLdValL(4) WDLdValM(4) WDStatL(4) WDStatM(4) SCLdVal0(4) Evt1PostMskSPI Evt1MskSPI IntPortSrc(5) IntPortSrc(4) Int2PostMskPort(7) Int2PostMskPort(6) Int1PostMskTim2 Int1PostMskTim3 Int1PostMskOpAmp Int2PostMskPort(5) IntPortSrc(3) Evt1StsSlpCnt Evt1PostMskADC WDKey(3) WDLdValL(3) WDLdValM(3) WDStatL(3) WDStatM(3) SCLdVal0(3) Int0PostMskPr1Ck0 Int0PostMskADC Int0PostMskDoCDM Int2MskPort(7) Int2MskPort(6) Int2MskPort(5) Int1MskTim2 Int1MskTim3 Int1MskOpAmp Int0MskPr1Ck0 Int0MskADC Int0MskDoCDM Int0MskDoCPM Int1MskPr1Ck5/3 Int2MskPort(4) Int0PostMskDoCPM Int1PostMskPr1Ck5/3 Int2PostMskPort(4) IntPortSrc(2) Evt1StsSPI Evt1MskADC WDKey(2) WDLdValL(2) WDLdValM(2) WDStatL(2) WDStatM(2) SCLdVal0(2) Int2StsPort(7) Int2StsPort(6) Int2StsPort(5) Int2StsPort(4) Int1StsTim2 Int1StsTim3 Int1StsOpAmp Int1StsPr1Ck5/3 Int0StsPr1Ck0 Int0StsADC Int0StsDoCDM Int0StsDoCPM Int0StsGasp Int1StsSPIStop Int2StsPort(3) Int0MskGasp Int1MskSPIStop Int2MskPort(3) Int0PostMskGasp Int1PostMskSPIStop Int2PostMskPort(3) IntPortSrc(1) Evt1StsADC Evt0PostMskGasp WDKey(1) WDLdValL(1) WDLdValM(1) WDStatL(1) WDStatM(1) SCLdVal0(1) VLDSelLvl(4) VLDSelLvl(3) VLDSelLvl(2) VLDSelLvl(1) VLDSelSrc(2) VLDSelSrc(1) VLDSelSrc(0) DC-DCLevel(0) DC-DCIdle DC-DCStartSts -
RegName
Address
Init.
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
VLDSelLvl(0) Int0StsPMMiss Int1StsSPIStart Int2StsTim4 Int0MskPMMiss Int1MskSPIStart Int2MskTim4 Int0PostMskPMMiss Int1PostMskSPIStart Int2PostMskTim4 IntPortSrc(0) Evt0StsGasp Evt0MskGasp WDClear WDKey(0) WDLdValL(0) WDLdValM(0) WDStatL(0) WDStatM(0) SCLdVal0(0)
www..com
RegDC-DCCfg
0x005D
0x00
EnDC-DC
RegVLDCfg1
0x005E
0x00
EnVLD
RegVLDCfg2
0x005F
0x00
-
RegBgrCfg
0x0060
0x00
BgrEnOut
RegInt0Sts
0x0061
0x00
Int0StsPort(0)
RegInt1Sts
0x0062
0x00
Int1StsPort(2)
RegInt2Sts
0x0063
0x00
Int2StsVLD
RegInt0Msk
0x0064
0x00
Int0MskPort(0)
RegInt1Msk
0x0065
0x00
Int1MskPort(2)
RegInt2Msk
0x0066
0x00
Int2MskVLD
RegInt0PostMsk
0x0067
0x00
Int0PostMskPort(0)
RegInt1PostMsk
0x0068
0x00
Int1PostMskPort(2)
RegInt2PostMsk
0x0069
0x00
Int2PostMskVLD
RegIntPortSrc
0x006A
0x00
IntPortSrc(7)
RegEvtSts
0x006B
0x00
-
RegEvtCfg
0x006C
0x00
Evt1PostMskSC
RegWDCfg
0x006D
0x00
WDDis
RegWDKey
0x006E
0x00
WDKey(7)
RegWDLdValL
0x006F
0x00
WDLdValL(7)
RegWDLdValM
0x0070
0x80
WDLdValM(7)
RegWDStatL
0x0071
0x00
WDStatL(7)
RegWDStatM
0x0072
0x80
WDStatM(7)
RegSCCfg
0x0073
0x00
SCDis
RegSCLdVal0
0x0074
0x00
SCLdVal0(7)
Copyright (c) 2010, EM Microelectronic-Marin SA 6819-DS, Version 3.0 ,8-Jul-10
24
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R
EM6819FX-A00X, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x
Bit6
SCLdVal1(6) SCLdVal2(6) SCStat0(6) SCStat1(6) SCStat2(6) SPIMode(2) SPISelSClk(0) SPIDIn(6) SPIDOut(6) CacheB00(6) CacheB01(6) CacheB02(6) CacheB03(6) CacheB04(6) CacheB05(6) CacheB06(6) CacheB07(6) CacheB08(6) CacheB09(6) CacheB10(6) CacheB11(6) CacheB12(6) CacheB13(6) CacheB12(5) CacheB13(5) CacheB11(5) CacheB10(5) CacheB09(5) CacheB08(5) CacheB07(5) CacheB07(4) CacheB08(4) CacheB09(4) CacheB10(4) CacheB11(4) CacheB12(4) CacheB13(4) CacheB06(5) CacheB06(4) CacheB05(5) CacheB05(4) CacheB04(5) CacheB04(4) CacheB03(5) CacheB03(4) CacheB02(5) CacheB02(4) CacheB02(3) CacheB03(3) CacheB04(3) CacheB05(3) CacheB06(3) CacheB07(3) CacheB08(3) CacheB09(3) CacheB10(3) CacheB11(3) CacheB12(3) CacheB13(3) CacheB01(5) CacheB01(4) CacheB01(3) CacheB00(5) CacheB00(4) CacheB00(3) SPIDOut(5) SPIDOut(4) SPIDOut(3) SPIDIn(5) SPIDIn(4) SPIDIn(3) SPIDIn(2) SPIDOut(2) CacheB00(2) CacheB01(2) CacheB02(2) CacheB03(2) CacheB04(2) CacheB05(2) CacheB06(2) CacheB07(2) CacheB08(2) CacheB09(2) CacheB10(2) CacheB11(2) CacheB12(2) CacheB13(2) SPISelSIn(1) SPISelSIn(0) SPIMode(1) SPIMode(0) SPINegEdg SPIRTO SCStat2(5) SCStat2(4) SCStat2(3) SCStat2(2) SCStat1(5) SCStat1(4) SCStat1(3) SCStat1(2) SCStat0(5) SCStat0(4) SCStat0(3) SCStat0(2) SCStat0(1) SCStat1(1) SCStat2(1) SPIMSB1st SPIDIn(1) SPIDOut(1) CacheB00(1) CacheB01(1) CacheB02(1) CacheB03(1) CacheB04(1) CacheB05(1) CacheB06(1) CacheB07(1) CacheB08(1) CacheB09(1) CacheB10(1) CacheB11(1) CacheB12(1) CacheB13(1) SCLdVal2(5) SCLdVal2(4) SCLdVal2(3) SCLdVal2(2) SCLdVal2(1) SCLdVal1(5) SCLdVal1(4) SCLdVal1(3) SCLdVal1(2) SCLdVal1(1)
RegName
Address
Init.
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCLdVal1(0) SCLdVal2(0) SCStat0(0) SCStat1(0) SCStat2(0) SPIAutoStart SPIDIn(0) SPIDOut(0) CacheB00(0) CacheB01(0) CacheB02(0) CacheB03(0) CacheB04(0) CacheB05(0) CacheB06(0) CacheB07(0) CacheB08(0) CacheB09(0) CacheB10(0) CacheB11(0) CacheB12(0) CacheB13(0)
www..com
RegSCLdVal1
0x0075
0x80
SCLdVal1(7)
RegSCLdVal2
0x0076
0x00
SCLdVal2(7)
RegSCStat0
0x0077
0x00
SCStat0(7)
RegSCStat1
0x0078
0x80
SCStat1(7)
RegSCStat2
0x0079
0x00
SCStat2(7)
RegSPICfg1
0x007A
0x03
SPIEn
RegSPICfg2
0x007B
0x00
SPISelSClk(1)
RegSPIStart
0x007C
0x00
SPIStart
RegSPIDIn
0x007D
0x00
SPIDIn(7)
RegSPIDOut
0x007E
0x00
SPIDOut(7)
RegCacheB00
0x0280
0x00
CacheB00(7)
RegCacheB01
0x0281
0x00
CacheB01(7)
RegCacheB02
0x0282
0x00
CacheB02(7)
RegCacheB03
0x0283
0x00
CacheB03(7)
RegCacheB04
0x0284
0x00
CacheB04(7)
RegCacheB05
0x0285
0x00
CacheB05(7)
RegCacheB06
0x0286
0x00
CacheB06(7)
RegCacheB07
0x0287
0x00
CacheB07(7)
RegCacheB08
0x0288
0x00
CacheB08(7)
RegCacheB09
0x0289
0x00
CacheB09(7)
RegCacheB10
0x028A
0x00
CacheB10(7)
RegCacheB11
0x028B
0x00
CacheB11(7)
RegCacheB12
0x028C
0x00
CacheB12(7)
RegCacheB13
0x028D
0x00
CacheB13(7)
Copyright (c) 2010, EM Microelectronic-Marin SA 6819-DS, Version 3.0 ,8-Jul-10
25
www.emmicroelectronic.com
R
EM6819FX-A00X, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x
Bit6
CacheB14(6) CacheB15(6) CacheB16(6) CacheB17(6) CacheB18(6) CacheB19(6) CacheB20(6) CacheB21(6) CacheB22(6) CacheB23(6) CacheB24(6) CacheB25(6) CacheB26(6) CacheB27(6) CacheB28(6) CacheB29(6) CacheB30(6) CacheB31(6) TrimOsc15M(6) TrimOsc2M(6) StsCSReson TrimOsc2M(5) TrimOsc15M(5) CacheRow(5) CacheB31(5) CacheB31(4) CacheRow(4) TrimOsc15M(4) TrimOsc2M(4) StsCSXtal CacheB30(5) CacheB30(4) CacheB29(5) CacheB29(4) CacheB28(5) CacheB28(4) CacheB27(5) CacheB27(4) CacheB26(5) CacheB26(4) CacheB26(3) CacheB27(3) CacheB28(3) CacheB29(3) CacheB30(3) CacheB31(3) CacheRow(3) TrimOsc15M(3) TrimOsc2M(3) TrimVLD(3) StsCSPad CacheB25(5) CacheB25(4) CacheB25(3) CacheB24(5) CacheB24(4) CacheB24(3) CacheB23(5) CacheB23(4) CacheB23(3) CacheB22(5) CacheB22(4) CacheB22(3) CacheB21(5) CacheB21(4) CacheB21(3) CacheB21(2) CacheB22(2) CacheB23(2) CacheB24(2) CacheB25(2) CacheB26(2) CacheB27(2) CacheB28(2) CacheB29(2) CacheB30(2) CacheB31(2) CacheRow(2) CacheSector(2) TrimOsc15M(2) TrimOsc2M(2) TrimVLD(2) StsCSRC8k CacheB20(5) CacheB20(4) CacheB20(3) CacheB20(2) CacheB19(5) CacheB19(4) CacheB19(3) CacheB19(2) CacheB18(5) CacheB18(4) CacheB18(3) CacheB18(2) CacheB17(5) CacheB17(4) CacheB17(3) CacheB17(2) CacheB16(5) CacheB16(4) CacheB16(3) CacheB16(2) CacheB16(1) CacheB17(1) CacheB18(1) CacheB19(1) CacheB20(1) CacheB21(1) CacheB22(1) CacheB23(1) CacheB24(1) CacheB25(1) CacheB26(1) CacheB27(1) CacheB28(1) CacheB29(1) CacheB30(1) CacheB31(1) CacheRow(1) CacheSector(1) TrimOsc15M(1) TrimOsc2M(1) TrimVLD(1) StsCSRC2M CacheB15(5) CacheB15(4) CacheB15(3) CacheB15(2) CacheB15(1) CacheB14(5) CacheB14(4) CacheB14(3) CacheB14(2) CacheB14(1)
RegName
Address
Init.
Bit7
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CacheB14(0) CacheB15(0) CacheB16(0) CacheB17(0) CacheB18(0) CacheB19(0) CacheB20(0) CacheB21(0) CacheB22(0) CacheB23(0) CacheB24(0) CacheB25(0) CacheB26(0) CacheB27(0) CacheB28(0) CacheB29(0) CacheB30(0) CacheB31(0) CacheRow(0) CacheSector(0) TrimOsc15M(0) TrimOsc2M(0) TrimVLD(0) StsCSRC15M
RegCacheB14
0x028E
0x00
CacheB14(7)
RegCacheB15
0x028F
0x00
CacheB15(7)
RegCacheB16
0x0290
0x00
CacheB16(7)
RegCacheB17
0x0291
0x00
CacheB17(7)
RegCacheB18
0x0292
0x00
CacheB18(7)
RegCacheB19
0x0293
0x00
CacheB19(7)
RegCacheB20
0x0294
0x00
CacheB20(7)
RegCacheB21
0x0295
0x00
CacheB21(7)
RegCacheB22
0x0296
0x00
CacheB22(7)
RegCacheB23
0x0297
0x00
CacheB23(7)
RegCacheB24
0x0298
0x00
CacheB24(7)
RegCacheB25
0x0299
0x00
CacheB25(7)
RegCacheB26
0x029A
0x00
CacheB26(7)
RegCacheB27
0x029B
0x00
CacheB27(7)
RegCacheB28
0x029C
0x00
CacheB28(7)
RegCacheB29
0x029D
0x00
CacheB29(7)
RegCacheB30
0x029E
0x00
CacheB30(7)
RegCacheB31
0x029F
0x00
CacheB31(7)
RegCacheCfg1
0x02A0
0x00
-
RegCacheCfg2
0x02A1
0x80
NVMFastProg
RegTrimOsc15M
0x02A2
0x80
TrimOsc15M(7)
RegTrimOsc2M
0x02A3
0x80
TrimOsc2M(7)
RegTrimVLD
0x02A4
0x08
-
RegStsCStart
0x02A5
0x39
-
RegName
CkSwStsX -
Address
Init.
Bit7
Bit6
Bit5
CkSwSelHi(2) CkSwSelLo(2)
Bit4
StsEnReson CkSwSelHi(1) CkSwSelLo(1)
Bit3
StsEnXtal CkSwSelHi(0) CkSwSelLo(0)
Bit2
StsEnRC8k CkSwStsHi(2) CkSwStsLo(2)
Bit1
StsEnRC2M CkSwStsHi(1) CkSwStsLo(1)
Bit0
RegStsEnOsc
0x02A6
0x06
-
StsEnRC15M CkSwStsHi(0) CkSwStsLo(0)
RegCkSw1
0x02A7
0x12
CkSwSelX
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RegCkSw2
0x02A8
0x24
-
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EM6819FX-A00X, EM6819Fx-A10x EM6819Fx-B00x, EM6819Fx-B10x
2.6 PORT TERMINAL CONNECTION REFERENCE TABLE
Reset & WkUp VREF VLD OPAMP SPI GASP CLOCK Timer clock Timer start PWM high FrqOut drive
chip Nbr
Name
Base
IRQ
ADC
VSS protection pad to reduce double bond main VSS SCLK SOUT GASP-SCK GASP-SIO ADC0 Rst_Wkup0 ADC1 ADC2 Rst_Wkup1 ADC3 VLD VLD VLD OPA_INM SIN SOUT OPA_INM SOUT OPA_INP OPA_INP SIN OPA_Out OPA_Out t1ck0_in start1_in t2ck0_in start2_in t2ck1_in start3_in t3ck0_in start4_in t4ck0_in start5_in t4ck1_in start6_in HD HD HD HD HD HD
1 2 3 4 5 6 7 8 9 10 11 12
VSS2 VSS PB2 PB3 PB4 PB5 PB6 PB7 PA0 PC0 PA1 PC1
SUP SUP IO IO IO IO IO IO IO IO IO IO
PAIRQ0 PCIRQ0 PAIRQ1 PCIRQ1
sig sig sig sig sig sig sig sig sig sig sig sig sig sig sig sig
13 PA2
IO
PAIRQ2 ADC4 Rst_Wkup2 Vref_ADC
14 15 16 17 18
PC2 PA3 PC3 VREG PA4
IO IO IO SUP IO
PAIRQ2 ADC5 PAIRQ3 ADC6 Rst_Wkup3 PCIRQ3 ADC7 use external Capacitor PAIRQ4 Rst_Wkup4
HD HD
19 PC4 Rst_Wkup5
IO
PCIRQ4 GASP-Sel
XIN XOUT ExtCk
t1ck1_in start7_in
PAIRQ5 PCIRQ5 PCIRQ6 PAIRQ6 PAIRQ7 PCIRQ7 Rst_Wkup6 Vref_out Rst_Wkup7 VLD VLD VLD VLD
SCLK SCLK SOUT SIN
HD HD HD HD HD t3ck1_in HD HD
20 21 22 23 24 25 26 27 28 29 30 31 32
TM PA5 PC5 PC6 PA6 PA7 PC7 PB0 PB1 VSUP VSUP2 DCDC VSSDCDC
IN IO IO IO IO IO IO IO IO SUP SUP SUP SUP
sig sig sig sig sig sig sig sig
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VSUP protection pad to reduce noise DCDC Coil connection in case of DCDC Version, open (not bonded, if no DCDC) VSS for DCDC, not bonded for non DCDC versions
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2.7 TSSOP PACKAGE PINOUT CIRCUIT WITHOUT DC-DC AND S08
EM6819
EM6819
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EM6819
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EM6819
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2.8 TSSOP PACKAGE PINOUT CIRCUIT WITH DC-DC
EM6819 DCDC
EM6819 DCDC EM6819 DCDC
29 www.emmicroelectronic.com
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2.9 QFN PACKAGES WITH AND WITHOUT DCDC
with DCDC
20 Lead QFN 4x4mm body EM6819FX-AXXX
VSS2 PB6 PB5 PB4 PB3 PB2 VSS
27 26
32 Lead QFN 5x5mm body EM6819FX-AXXX
VSS2
25
PB6
PB4
PB2
20 32 31 30 29 28
19
18
VSS
17
16
VSS_ DC-DC
24
PB7 DCDC VSUP2 VSUP PB1 PB0 PC7 PA7 PA6 PA0
2 23 3 22
1
PB7 1
15
VSS_ DC-DC DC-DC PA1
4 21
PA1
2 14
PC0
PA2
3 13
VSUP2 PC1
5 20 6 19
PC2
4 12
EM6819 DCDC
VSUP PC2
7 18
PA2
EM6819 DCDC
17
PA3
5 11
PA6 PA3
8 9 10 11 12 13 14 15 16
6
7
8
9
10
PC3
PA4
PC4 TM
PA5
PC5
PC4
TM
PA4
PC6
without DCDC
20 Lead QFN 4x4mm body EM6819FX-BXXX
PB5 PB4 PB3 PB2 VSS
VREG
20
19
18
17
16
PB6
15
1 VSUP PB0 PA6 PC6 PC5
11 2 14
PB7 PA1
3
EM6819
12
13
PA2
4
PC2
5
6
7
8
9
10
PA4
PA3
Vreg
PC4
TM
VREG
PC6
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 3. CPU CORE CR816
Unlike most RISC processors, the CR816L provides instructions which can perform arithmetic and logical operations with operands stored either in the data memory or in internal registers. Similarly to classic 8-bit processors, the CR816L architecture provides an accumulator located at the ALU output that stores the last ALU result. All arithmetic operations support both signed and unsigned operations.
The full detail of the used CoolRISC 816L core is described in [1]. A brief overview of its highlights is given below. 8-bits RISC register-memory processor based on a Harvard architecture 3 stage pipeline (no delay slots or branch delays) 176 Kbytes max Program Memory size (64 KInstruction, 22 bit wide) 64 Kbytes max Data Memory size (organized in 256 x 256 Kbytes pages) 8 max hardware subroutines and unlimited software subroutines 8 bit x 8 bit hardware multiplier 5 addressing modes o direct addressing o indexed addressing with immediate offset o indexed addressing with register offset o indexed addressing with postincrementation of the offset o indexed addressing with predecrementaion of the offset 16 CPU internal registers (Accu, general purpose, Index, offset, status) The Instruction Set is composed of Branch Instructions Transfer Instructions Arithmetic and Logical Instructions Special Instructions
3.1 PM_MISS FUNCTION (FLASH READ MONITOR)
In extreme conditons (very low temperature and ck_hi > 15MHz) the NVM time access could be longer than a CPU cycle. In this case a pm_miss is generated, meaning that the CPU will automatically wait an additional cycle before to fetch the current instruction read in the NVM. Doing so, it guaranttees that the system never fails even if the CPU is running faster than the NVM. Interrupt of priority 0 Int0StsPmMiss is generated on each pm_miss.
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 4. NVM MEMORY
4.1 INTRODUCTION
The circuits Non Volatile Memory (NVM) is used to store the application software but it may also be used to store data (constants or variables). The same physical memory area is shared between the instruction code and the data's. The boundary in this general purpose NMV memory (GPNVM) between the instruction code and the data's is not fixed in detail by hardware but given by the linker after compilation. The data read access in NVM (see chapter "Read data in NVM") is executed as a simple register access. The data write access in NVM (see chapter "Write data in NVM") is not executed with a simple MOVE. It is necessary to store the data's in an intermediate memory called RAM cache and to execute an API sub-routine in the ROM. NVM data read access needs 2 CPU cycles, 1st the read instruction followed with an NVM data access. During the date access phase the CPU is in a wait state. The CR816 instruction is a 22 bits wide bus. When the CPU reads the NVM through the data's bus, 22 bits are read but only 2 bytes (16-bits) are accessed (the other 6 bits are used for verification). Note: If the additional 6 bits are not equal to 0x3F, the read access to the previous read pair of bytes is denied. The system interprets this access as a forbidden access to the program memory area (code protection feature) Instruction read by CPU is straight foreward; all instruction read take 1 CPU cycle.
4.2 NVM ARCHITECTURE
The NVM is divided in 6 sectors, each sector is devided in 64 rows and each row contains either 16 instructions or 32 data bytes. A single row shall not share instructions and data bytes. From the CPU data bus interface point of view, the NVM is mapped from address 0x4000 to 0x6FFF as shown in the following diagram. Figure 3, NVM architecture
Note: The row 63 and 62 of sector 5 is reserved for trimming word and unique ID code. Write access in this row is denied. The row 61 of sector 5 is used for NVM memory dump and external read/write access protection.
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4.3 RAM CACHE
The RAM cache is an image of 1 row of the NVM. The write access to the NVM is done row by row. After selecting the row and the sector to access, the RAM cache contents are copied in the selected row by the CPU executing a CALL of the API sub-routine in the ROM. The RAM cache is mapped as follows: DM address (HEX) 0x0280 0x0281 0x0282 0x0283 0x0284 0x0285 0x0286 0x0287 0x0288 0x0289 0x028A 0x028B 0x028C 0x028D 0x028E 0x028F 0x0290 0x0291 0x0292 0x0293 0x0294 0x0295 0x0296 0x0297 0x0298 0x0299 0x029A 0x029B 0x029C 0x029D 0x029E 0x029F
RAM cache byte RegCacheB00 RegCacheB01 RegCacheB02 RegCacheB03 RegCacheB04 RegCacheB05 RegCacheB06 RegCacheB07 RegCacheB08 RegCacheB09 RegCacheB10 RegCacheB11 RegCacheB12 RegCacheB13 RegCacheB14 RegCacheB15 RegCacheB16 RegCacheB17 RegCacheB18 RegCacheB19 RegCacheB20 RegCacheB21 RegCacheB22 RegCacheB23 RegCacheB24 RegCacheB25 RegCacheB26 RegCacheB27 RegCacheB28 RegCacheB29 RegCacheB30 RegCacheB31
4.4 WRITE DATA IN NVM
Only erased memory space can be written. Write applies always to one full row. Erase and write operation are handled by API-subroutines.
4.4.1
ROW AND SECTOR SELECTION
Write access is done row by row (32 bytes at a time). The row selection needs to be done before calling the API subroutine. RegCacheCfg1[5:0] in address 0x02A0 is the row pointer from, it may take values from 0x00 and 0x3F (row 63). RegCacheCfg2[2:0] in address 0x02A1 is the sector pointer, it may take values from 0x00 and 0x05.
4.4.2
FAST/SLOW OPERATION
In low voltage conditions (VSUPLow in register RegSysCfg1 = `1') all erase and write accesses to the NVM should be done using the corresponding erase_x_slow_x and write_x_slow_x API subroutine. The `slow' API routines will take more time to execute but will draw instantly less current.
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4.4.3 ERASE
Erase is a mandatory step before write. The NVM erase state is high, write state low. Only Row erase or sector erase are allowed, below table summaries the available API routines sub-routines erase_sector_apl erase_sector_slow_apl erase_row_apl Description Erase the selected sector [4:0]. Erase sector 5 is denied. Erase the selected sector [4:0] in slow mode. Erase sector 5 is denied. Erase the selected row [63:0] in the selected sector [5:0]. Erase row 63 & 62 in sector 5 is denied. Erase the selected row [63:0] in the selected sector [5:0] in slow mode. Erase row 63 & 62 in sector 5 is denied. Duration 2 ms 3 ms 2 ms
erase_row_slow_apl
3 ms
Accessing above routines will use the sector and row pointers as defined in RegCacheCfg2,1
4.4.4
WRITE
Before writing a specific row, the RAM cache needs to get the new data, the sector and row pointers need to be set according to the desired NVM location, and once everything setup, the CPU may call one of the below listed API subroutines to write the NVM row. Write access is row by row only. Write_row_x API routines include also the erase row. It is therefore not necessary to erase the row before. Write_only_x routines do not include the erase. These routines may only be used if the addressed row was erased earlier. sub-routines Description Duration Erase and write the selected row [63:0] in the selected sector [5:0]. 3 ms write_row_apl Access row 63 & 62 in sector 5 is denied. Erase and write the selected row [63:0] in the 4.5 ms write_row_slow_apl selected sector [5:0] in slow mode. Access row 63 & 62 in sector 5 is denied. Only write the selected row [63:0] in the selected 1 ms write_only_apl sector [5:0]. Write row 63 & 62 in sector 5 is denied. Only write the selected row [63:0] in the selected sector [5:0] in slow mode. 1.5 ms write_only_slow_apl Write row 63 & 62 in sector 5 is denied. Note: It is not allowed to re-write more a given row without prior erase
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4.5 ROW 61 SECTOR 5
It is possible to protect the NVM against undesired external access through the GASP interface. There are two kind of protection: Lock: No code or data modification from GASP are allowed; Sector and row erase, write_row and write_only are impossible. Specific GASP reads remain possible in specific user authorized areas. TLock: Same as Lock but in addition: It's impossible to analyse the NVM data over the GASP interface even with the factory test modes. TLock and Lock are bytes store in row 61 of sector 5. TLock is at address 0x6FDF (RegCacheB31) and 0x6FDE (RegCacheB30). They are active (NVM protected) when they are equal to 0x4E. As mentioned above, it is possible to open external access (GASP access) in read mode in a part of the NVM. The start and stop address of this window is stored in the row 61 of sector 5. The stop and start address are mapped as follows: Limit DM address RAM cache Start address MSB 0x6FDD RegCacheB29 Start address LSB 0x6FDC RegCacheB28 Stop address MSB 0x6FDB RegCacheB27 Stop address LSB 0x6FDA RegCacheB26 The rest of the row 61 of sector 5 is reserved and shall not be accessed by the user.
4.6 ROW 62 SECTOR 5
The row 62 of sector 5 contains different trimming values that are not copied automatically after reset but available to the user. The structure of this row is as follows: DM Address Mapped in RAM cache Function 0x6FDF:D2 RegCacheB31:16 Reserved 0x6FD1 RegCacheB17 Contains MSB[10:8] of ADC offset trim with range 3/8 0x6FD0 RegCacheB16 Contains LSB[7:0] of ADC offset trim with range 3/8 0x6FCF RegCacheB15 Contains MSB[10:8] of ADC offset trim with range 4/8 0x6FCE RegCacheB14 Contains LSB[7:0] of ADC offset trim with range 4/8 0x6FCD RegCacheB13 Contains MSB[10:8] of ADC offset trim with range 6/8 0x6FCC RegCacheB12 Contains LSB[7:0] of ADC offset trim with range 6/8 0x6FCB RegCacheB11 Contains MSB[10:8] of ADC offset trim with range 8/8 0x6FCA RegCacheB10 Contains LSB[7:0] of ADC offset trim with range 8/8 0x6FC9 RegCacheB9 Contains MSB[10:8] of ADC offset using temperature sensor 0x6FC8 RegCacheB8 Contains LSB[7:0] of ADC offset using temperature sensor 0x6FC7:C6 RegCacheB7:6 Reserved 0x6FC5 RegCacheB5 Contains MSB[10:8] of temperature sensor result at 60C 0x6FC4 RegCacheB4 Contains LSB[7:0] of temperature sensor result at 60C 0x6FC3 RegCacheB3 Contains MSB[10:8] of temperature sensor result at 25C 0x6FC2 RegCacheB2 Contains LSB[7:0] of temperature sensor result at 25C 0x6FC1 RegCacheB1 Contains RC 15MHz trimming value at 60C 0x6FC0 RegCacheB0 Contains RC 2MHz trimming value at 60C The user can not update the values in sector 5 row 62, write access is denied.
4.6.1
TEMPERATURE TOLERANCE
Above calibration values are measured under the following temperature tolerances: Nominal temperature Tolerance 25C -3C / +5C 60C +/- 3C Note: These tolerances have no influence on the RC temperature compensation procedure. It depends only on the linearity of the RC trim and temperature sensor.
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4.7 ROW 63 SECTOR 5
The row 63 of sector 5 contains the different trimming values used by the system to position the device at power-up and after each reset. It contains also one unique ID code and a CRC code of the row to check at any time the data integrity of this row.. The structure of this row is as follows: DM Address Mapped in RAM cache Function 0x6FFF:FE RegCacheB31:30 Reserved 0x6FFD RegCacheB29 Contains RC 15MHz oscillator trimming byte @ 25C 0x6FFC RegCacheB28 Contains RC 2MHz oscillator trimming byte @ 25C 0x6FFB:FA RegCacheB27:26 Reserved 0x6FF9 RegCacheB25 Contains VLD trimming value 0x6FF8:F3 RegCacheB24:19 Reserved 0x6FF2:F1 RegCacheB18:17 CRC calculated on 29:19,14 0x6FF0:EB RegCacheB16:11 Reserved 0x6FEA:E4 RegCacheB10:4 Unique ID code 0x6FE3:E0 RegCacheB3:0 Reserved The user can not update the values in sector 5 row 63 & 62, write access is denied.
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4.8 READ DATA IN NVM
Read access to NVM memory is done like a register read access. However only data values may be read, any access to instruction code through the data memory bus in read mode is denied. The limit between data values and instruction code is defined by the linker during compilation. As it is mentioned above, the NVM is mapped in possible data memory areas as follows: Sector 0 1 2 3 4 5 DM address (HEX) 0x4000 to 0x47FF 0x4800 to 0x4FFF 0x5000 to 0x57FF 0x5800 to 0x5FFF 0x6000 to 0x67FF 0x6800 to 0x6FFF
When NVM is accessed through the data memory bus, the execution of software is stopped during one cycle (wait state) as the data memory is shared with program memory. Reading NVM accesses always 22 bits split in three elements (2 bytes and 6bits). The two bytes are stored in a buffer; the 6 additional bits discarded. If this pair of bytes is accessed successively, the data memory buffer is read directly and the NVM is not accessed (no wait cycle).
4.9 ROW TO CACHE
When the user wants to change one byte or even one bit in the NVM, he has to write the entire row where the modification has to be done. To simplify this procedure, a sub-routine able to dump one full row to the RAM chache exists: nvm_to_cache_apl. The user has to specify the row (RegCacheCfg1) and the sector (RegCacheCfg2) pointers. After modifying the byte or the bit directly in the RAM cache he can write it's contents back into the NVM using sub-routine write_row_apl. Figure 4, Row to Cache flowchart
Select the row RegCacheCfg1[5:0]
Select the sector RegCacheCfg2[2:0]
Dump NVM row into RAM cache Sub_routine: nvm_to_cache_apl
Modify the RAM cache content
Write RAM cache in NVM back Sub_routine: write_row_apl
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4.9.1
NVM CONFIGURATION REGISTERS
RegCacheCfg1 Type ResVal NI RW 0x00 ResSrc ResSys NVM Row Cache Configuration - 1 Description Not implemented NVM Row Cache: Row number of Sector (CacheSector)
0x02A0 Bits Name 7:6 5:0 CacheRow
0x02A1 RegCacheCfg2 NVM Row Cache Configuration - 2 Bits Name Type ResVal ResSrc Description 7 NVMFastProg RW 1 ResSys NVM fast programming mode 2:0 CacheSector RW '000' ResSys NVM Row Cache: Sector number Note: The bit NVMFAstProg is automatically set in the ROM API routine. It is set to `0' automatically when a slow operation is called, otherwise it is set to `1'. 0x0280 to 0x029F Bits Name 7:0 CacheB00 ... 7:0 CacheB31 RegCacheB00 to RegCacheB31 Type ResVal RW 0x00 ... ... RW 0x00 NVM Row Cache Byte-0 to NVM Row Cache Byte-31 Description NVM Row Cache Byte-0 ... NVM Row Cache Byte-31
ResSrc ResSys ... ResSys
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5.1 CRC CHECK ON PROGRAM AREA
It is possible, at any time, to check the content of the NVM by calculating the CRC on the program memory. A subroutine dedicated for this procedure exists: calc_crc_code_apl. The start and stop address of the area to check shall be given as parameter to the sub-routine as follows: Parameter Location (CPU Index registers) CRCStartAddrMSB r3 CRCStartAddrLSB r2 CRCStopAddrMSB r1 CRCStopAddrLSB r0 CRCStopAddr shall be higher to CRCStartAddr otherwise the routine fails and the result is not guaranteed. The full NVM memory range in program memory area is mapped as follows: Sector PM address (HEX) 0 0x0000 to 0x03FF 1 0x0400 to 0x07FF 2 0x0800 to 0x0BFF 3 0x0C00 to 0x0FFF 4 0x1000 to 0x13FF 5 0x1400 to 0x17FF The CRC made on program memory checks all the content of the NVM including the 6 additional bits that are not accessed through the data memory bus. Note: The user can make a CRC on the full NVM including the row 63 & 62 of sector 5. But in this case the CRC will not be constant between different devices.
5.2 CRC CHECK ON DATA AREA
It is possible, at any time, to check the content of the NVM by calculating the CRC on the data memory area. A subroutine dedicated for this procedure exists: calc_crc_code_apl. The start and stop address of the area to check shall be given as parameter to the sub-routine as follows: Parameter Location (CPU Index registers) CRCStartAddrMSB r3 CRCStartAddrLSB r2 CRCStopAddrMSB r1 CRCStopAddrLSB r0 CRCStopAddr shall be higher to CRCStartAddr otherwise the routine fails and the result is not guaranteed. The full NVM memory range in data memory area is mapped as follows: Sector DM address (HEX) 0 0x4000 to 0x47FF 1 0x4800 to 0x4FFF 2 0x5000 to 0x57FF 3 0x5800 to 0x5FFF 4 0x6000 to 0x67FF 5 0x6800 to 0x6FFF The CRC made on data memory does not check all the content of the NVM because it excludes the 6 additional bits. It should be used to check constant tables for instance and not the program code integrity. The CRC calculation on data is also possible in the RAM area which is mapped on the following addresses: Block RAM DM address (HEX) 0x0080 to 0x027F
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System Boot sequence Erase/write operation in NVM Dump NVM row into RAM cache CRC calculation on NVM or RAM ISP functions (Program loading, CRC check)
The circuit has a ROM memory used for the following purposes: Refer also to [2].
6.1 BOOT SEQUENCE
This sequence runs after any reset. Depending on the reset source, the boot sequence can change as follows: Reste source Start-up Power-Down wakeup VSUP Low (1.0V) Start-up Power-Down wakeup VSUP High (2.5V) ResAna ResSys Description Power-up (voltage-multiplier rising up and power check) All trimming value are copied from NVM into the related registers Power-up (power check) All trimming value are copied from NVM into the related registers All trimming value are copied from NVM into the related registers No trimming value are copied from NVM into the related registers. Duration 7 ms
5 ms
3.5 ms 1 ms
At the end of the boot sequence the watchdog is cleared. The user application software starts. All registers have the value as described in the register map depending what reset source is the cause of the boot sequence.
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6.2 SUB-ROUTINES USED FOR APPLICATION
Using sub-routine in ROM API has an impact on the execution time and the memory. The following table shows for each application routine the number of CPU instructions needed to execute the sub-routine and the addresses in RAM memory used by the sub-routine "software stack" that cannot be recovered. ROM API sub-routine does not use any fixed RAM address for parameter storage. All local variables needed by any of the application sub-routine are stored on the software stack, thus the application programmer shall ensure that: 1. The software stack pointer points to the RAM before any call of the application routine. The software stack pointer is i3 register of CR816. The i3 stack pointer is not initialised by the ROM SW boot sequence. It is under the programmer responsibility to initialise it after boot sequence. 2. The application does not use the the memory in range i3 points too. Depending on the sub-routine, this range can be from i3-21 to i3. All data stored in this range before calling the sub-routine may be lost. It is advised to reserve 22 bytes for software stack in RAM to ensure that any sub-routine will never erase important data. Routine name cacl_crc_code_apl cacl_crc_data_apl erase_row_apl erase_row_slow_apl erase_sector_apl erase_sector_slow_apl nvm_to_cache write_only_apl write_only_slow_apl write_row_apl write_row_slow_apl get_def get_trim Stack requirements (bytes) 12 bytes 10 bytes 22 bytes 22 bytes 22 bytes 22 bytes 14 bytes 22 bytes 22 bytes 22 bytes 22 bytes Execution time 11.2N + 66 (-3% ; +7%) instructions
N = stop_address - start_address + 1
6N + 64 (-4% ; +3%) instructions
N = stop_address - start_address + 1
2 ms (no fixed number of instruction) 3 ms (no fixed number of instruction) 2 ms (no fixed number of instruction) 3 ms (no fixed number of instruction) 351 instructions 1 ms (no fixed number of instruction) 1.5 ms (no fixed number of instruction) 3 ms (no fixed number of instruction) 4.5 ms (no fixed number of instruction) Copy's row 63 in RAM cache Copy's row 62 in RAM cache
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RAM memory size is 512 bytes mapped in the data memory bus. It can be divided in two parts: the first part accessible with direct addressing instruction and the second part not accessible by direct addressing instructions as describe on the following table: DM address (HEX) Addressing 0x0080 to 0x00FF Direct (128 Bytes) 0x0100 to 0x0280 Indirect (384 Bytes) In any condition the RAM is accessed in a single CPU cycle for write and read access. Note: For any information concerning the direct and indirect addressing, refer to the CR816-DL documentation.[1]
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The reset controller collects all different reset sources and initializes the needed peripheral registers. Refer to the individual peripheral register mapping tables to see which reset is initializing a specific register. Some of the reset sources are maskable to prevent undesired system reinitialization. After any reset the circuit will perform a power check and go to active mode. Then the reset status bits can be read to identify the reset source.
8.1 RESET SOURCES
Possible reset source signals are: POR Power on reset, non-maskable The fully internal POR cell will initialize the full circuit at power-up or if the supply voltge falls below VPOR voltage. PwrDown Power-Down mode In power down all internal registers are initialized, the pad configuration however may be locked to the last good state by setting LckPwrCfg=1 prior to Power-Down mode. User defined Port A terminal reset function, maskable. Any port A terminal may trigger reset. Watchdog timer reaching 0, maskable. Logic watchdog reset running on the internal 8kHz Oscillator. Brown out reset at low regulated voltage, maskable. CoolRISC bus error when trying to access non-valid instruction space, non-maskable. Entering Gasp modes (ISP, DoC), non-maskable. This reset initializes the circuit prior to programming or degugging.
ResPA
ResWD
ResBO ResBE ResGASP
8.2 RESET SIGNALS
A combination of the above mentioned reset sources is used to initialize the different peripheral registers. These reset signals are POR, PorLog, ResAna, ResSys.
8.2.1
POR
A small logic remains active even in Power-Down mode to allow wake-up. This logic is initialized by POR signal. In the user data memory space this concerns the bit LckPwrCfg.
8.2.2
PORLOG
PorLog signal will reinitialize all reset flags and all pullup/pulldown configuration bits PorLog = Por OR PwrDown (logical OR combination)
8.2.3
RESANA
ResAna signal will initialize all reset enable bits, the port A input and output enable bits, the port A debouncer selection bits, all trim bits and the analog configuration settings for the DC-DC and Opamp. ResAna = Por OR PwrDown OR ResWD OR ResBE (logical OR combination)
8.2.4
RESSYS
ResSys signal initializes all remaining data memory registers, except the RAM which needs to be initialized by the user software if needed. ResSys = Por OR PwrDown OR ResWD OR ResBE OR ResPA OR ResGasp OR ResBO
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8.2.5 RESET FLAGS
All reset flags are in the Reset flag register: RegResFlg and placed as follows The ResFlgPA bit is asserted by reset from PortA. The ResFlgWD bit is asserted by reset from Watchdog. The ResFlgBO bit is asserted by reset from Brownout. The ResFlgGasp bit is asserted by reset from GASP. The ResFlgBE bit is asserted by reset from CoolRisc Bus-error detection. Note: To detect the Reset from Power-Down, the SW shall read the status of LckPwrCfg.
8.3 RESET REGISTERS
0x0000 Bits Name 7 SelSleep 6 SelPwrDwn 4 EnBrownOut 3:2 XtalCldStart 1 StdByFastWkUp 0 VSUPLow 0x0001 Bits Name 7:0 EnResPA 0x0006 Bits Name 7 ResFlgPA 6 ResFlgWD 5 ResFlgBO 4 ResFlgGasp 3 ResFlgBE 0 LckPwrCfg RegSysCfg1 Type ResVal RW 0 RW 0 RW 1 RW '00' RW 0 RO 0 RegEnResPA Type ResVal RW 0x00 RegResFlg Type ResVal ResFlg 0 ResFlg 0 ResFlg 0 ResFlg 0 ResFlg 0 RW 0 ResSrc ResSys ResSys ResAna ResSys ResSys System Configuration - 1 Description Select Sleep mode on Halt Select Power-Down mode on Halt Enable Brown Out Select Xtal Osc. ColdStart length Stand-by mode fast Wakeup VSUP is Low - Tripler activated Enable Reset by PortA bits Description Enable Reset by PortA bits Reset Flags Description Flag Reset from Port-A Flag Reset from WatchDog Flag Reset from Brown-Out Flag Reset from GASP Flag Reset from CoolRISC Bus-Error Lock configurations to be kept in Power-Down mode
ResSrc ResAna
ResSrc PorLog PorLog PorLog PorLog PorLog Por
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The circuit contains * 3 independent fully internal RC osillcators, * 15Mhz factory pretrimmed * 2Mhz factory pretrimmed * 8kHz * Either one of these external clock sources o 32 KHz watch crystal oscillator (Crystal extern). Mapped on terminals PA4, PC4. o 4 MHz Crystal or Resonator oscillator (Crystal or Resonator extern). Mapped on terminals PA4, PC4. o External high or Low frequency clock input. Mapped on terminal PC4. The oscillator source can be changed on the fly to always use the appropriate oscillator and clock setting according to the desired speed for i.e high speed calculation or low speed controlling, and hence optimise the power consumption. The circuit will always start-up on the 2MHz RC Oscillator. All circuit internal clocks are derived from the above mentioned oscillators. These clock sources may be predivided locally for optimum speed and power. Figure 5; oscillator and clock selection architecture
Hi-Freq trimmed RC Oscillators RC_15M RC_2M Ck_15M Ck_2M Ck_Hi
SelCkExt[1:0] PC4/OscOut
CkSwSelHi CkSwStsHi ReqCkHi/Lo
Oscillators and Clock selection
SelCkHi[1:0] SelCkCR[3:0]
/1/2/4/8 /16/32/64 /1/2/4/8
Ck_CR
CR816
CoolRISC
Ck_PC4
HF
SelCkPR2[2:0] LF
Ck_Reson Ck_Xtal32
Ck_Ext
Clock Synchro switch
CkSwStsX
/1/2/4/8
Pr2Ck[10:0]
Ck_Pr2 Prescaler2 10 stages
Clock source for Timer, SPI, Debouncer FreqOut
Pr1Ck[15:0]
PA4/OscIn
CkSwSelX
ReqCkHi/Lo
Resonator, 32kHz Crystal Ext Clock
SelCkPR1[2:0] SelCkLo[1:0]
/1/2/4/8
/4
Ck_Lo
ReqCkHi/Lo
Ck_Pr1 Prescaler1 15 stages
Clock source for RTC, Debouncer,Timer, SPI, IRQ, FreqOut
CkSwSelLo
CkSwStsLo
Lo-Freq RC Oscillator
RC_8k
Ck_8k
SCWakeUp Watchdog
/1/2/4/8 /16/32/64
Ck_ADC
10 bit ADC
The RC15Mhz Ck_15M and RC_2Mhz Ck_2M oscillators are factory pretrimmed, the RC_8kHz Ck_8k oscillator is the only clock source for the watchdog and the sleep counter reset function, but can also be used as a very low system clock. The RC_8kHz low frequency oscillator is not trimmed. On the PA4 and PC4 an external 32 KHz Crystal Ck_Xtal or 4MHz Resonator/Crystal Ck_Reson oscillator can be connected or one may have an external clock input Ck_PC4 on PC4. The selected output clock signal is Ck_Ext. The Ck_Hi clock signal can come from the 15MHz RC, 2MHz RC, 4MHz Resontor/Crystal or the external high frequency clock input on PC4. The Ck_Lo clock signal can come from the 32 KHz Crystal oscillator, divided 32 KHz, 8 kHz RC or the low frequency external clock on PC4; it is synchronized with the high frequency clock Ck_Hi if present. Ck_Lo clock synchronization
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with Ck_Hi allows fully synchronous circuit operation. The synchronization is disabled if the Ck_Hi or divided Ck_Hi clock is not used by any periphery. The CPU input clock Ck_CR is derived from either divided or undivided Ck_Hi or Ck_Lo. The Prescaler 1 Ck_Pr1 and Prescaler 2 CkPr2 input clock is derived fom either divided or undivided Ck_Hi or direct Ck_Lo. The ADC input clock Ck_ADC is derived from either divided or undivided Ck_Hi clock signal.
9.1 EXTERNAL CLOCK SELECTION
The External Component or Input clock source Ck_Ext is selected by register RegClockCfg1 bits SelCkExt as follows: SelCkExt 00 01 10 11 Input Ck_Xtal Ck_Reson Ck_PC4 Used PADs PA4, PC4 PA4, PC4 PC4, PCInpE[4]='1' Description No clock selection Xtal Resonator External Clock input Frequency none 32 KHz 4 MHz Min: Ck_Lo * 8; Max: 15 MHz Max: Ck_Hi / 8; Min: 0 Hz
Used for: Ck_Hi Used for: Ck_Lo
The default external clock source after system reset (ResSys) is "00" - None. The Ck_Ext clock signal is tied low. Before using an external clock input source one shall configure the necessary PA4 PC4 pads as analog inputs in case of external XTAL or Resonator, and as logic input with PCInpEn[4]=1 in case of external PC4 clock input. The external clock input on PC4 has min/max frequencies depending on its future use as Ck_Hi or Ck_Lo clock source; refer to the table above for the limits.
9.2 INTERNAL HIGH AND LOW FREQUENCY CLOCK SELECTION
The high Ck_Hi and low Ck_Low system frequencies can be selected independently but some restrictions for apply if connecting the external clock source. The High Frequency clock Ck_Hi is selected according to the register RegClockCfg1 bits SelCkHi as follows: SelCkHi Ck_Hi Source Select signal 00 Ck_15M SelRC15M 01 Ck_2M SelRC2M 10 Ck_Ext SelExt 11 Ck_2M SelRC2M The default Ck_Hi clock source after system reset (ResSys) is Ck_2M. The Low Frequency clock Ck_Lo is selected according to the register RegClockCfg1 bits SelCkLo as follows: SelCkLo Ck_Lo Source Select signal 00 Ck_Ext SelExt 01 Ck_Ext Divided by 4 (Ck_Ext/4) SelExt 10 Ck_8k SelRC8k 11 Ck_8k SelRC8k The default Ck_Lo clock source after system reset (ResSys) shall be Ck_8k. Note: If Ck_Hi or Ck_Lo are switched from external clock (SelExt active) to Ck_15M, Ck_2M or Ck_8k the SelCkExt selection must not be changed until the status bits for the selected Ck_Hi external clock RegCkSw1.CkSwStsHi or Ck_Lo external clock RegCkSw2.CkSwStsLo has changed to `0'
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9.2.1
EXTERNAL CLOCK SELECTION RESTRICTIONS
The external clock source selection for both high and low frequency clocks is very flexible, however some restrictions apply: The external clock must not be connected to both Ck_Hi and Ck_Lo at the same time. Allowed usage for external clock input on either high or low frequency domain: External Clock source SelCkExt Source 00 None 01 Xtal 10 11 Renonator PC4 Allowed configuration None Ck_Lo: (SelCkLo == 00 || SelCkLo == 01) && SelCkHi !=10 (Ck_Hi on RC Osc and Ck_Lo on either Ck_Ext or Ck_Ext/4) Ck_Hi: SelCkHi == 10 && (SelCkLo != 00 && SelCkLo != 01) (Ck_Hi on Ck_Ext and Ck_Lo on Ck_8k) Ck_Lo: (SelCkLo == 00 || SelCkLo == 01) && SelCkHi !=10 (Ck_Hi on RC Osc and Ck_Lo on either Ck_Ext or Ck_Ext/4 Ck_Hi: SelCkHi == 10 && (SelCkLo != 00 && SelCkLo != 01) (Ck_Hi on Ck_Ext and Ck_Lo on Ck_8k)
9.2.2
CPU CLOCK SELECTION
The CPU input clock Ck_CR is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different CPU clocking possibilities. The CPU clock divider selection is done in register RegClockCfg2 bits SelCkCR. SelCkCR 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CoolRisc Clock Ck_Hi (divided by 1) Ck_Hi divided by 2 Ck_Hi divided by 4 Ck_Hi divided by 8 (default) Ck_Hi divided by 16 Ck_Hi divided by 32 Ck_Hi divided by 64 Ck_Hi divided by 8 Ck_Lo (divided by 1) Ck_Lo divided by 2 Ck_Lo divided by 4 Ck_Lo divided by 8 Ck_Lo (divided by 1) Ck_Lo (divided by 1) Ck_Lo (divided by 1) Ck_Lo (divided by 1)
The default CR clock source after system reset (ResSys) is Ck_Hi divided by 8 (selection 0x3). The CPU instruction execution cycle corresponds to half the Ck_CR clock frequency. 2 MHz input clock results in 1 MIPS. ReqCkHi or ReqCkLo signals are asserted to the Hi- or Low frequency clock switches depending of the CR multiplexer selection.
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9.2.3 PRESCALER1 CLOCK SELECTION
The Prescaler1 input clock Ck_Pr1 is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different prescaler1 clocking possibilities. The prescaler clock divider selection is done in register RegClockCfg3 bits SelCkPr1. SelCkPr1 000 001 010 011 100 Others Prescaler1 Clock Ck_Hi (divided by 1) Ck_Hi divided by 2 Ck_Hi divided by 4 Ck_Hi divided by 8 default Ck_Lo (divided by 1) Ck_Hi divided by 8
The default Prescaler1 clock source after system reset (ResSys) shall be Ck_Hi divided by 8 (selection 0x3). ReqCkHi or ReqCkLo signals are asserted to the Hi- or Low frequency clock switches depending of the Prescaler1 multiplexer selection.
9.2.4
PRESCALER 2 CLOCK SELECTION
The Prescaler2 input clock Ck_Pr2 is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different prescaler1 clocking possibilities. The prescaler clock divider selection is done in register RegClockCfg3 bits SelCkPr2. SelCkPr2 000 001 010 011 100 Others 1xx Prescaler2 Clock Ck_Hi (divided by 1) Ck_Hi divided by 2 Ck_Hi divided by 4 Ck_Hi divided by 8 Ck_Lo (divided by 1) Ck_Lo (divided by 1)
The default Prescaler2 clock source after system reset (res_sys) shall be Ck_Lo divided by 1 (selection 0x4). ReqCkHi or ReqCkLo signals are asserted to the Hi- or Low frequency clock switches depending of the Prescaler2 multiplexer selection.
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9.3 CLOCK CONTROL
Ck_Hi and Ck_Lo are active only if needed. * If Ck_Hi is selected by any of SelCkCR, SelCkPr1, SelCkPr2, its ReqCkHi signal becomes active and the oscillator as selected by the SelCkHi-multiplexer will be enabled, otherwise it shall be disabled. The oscillator is also enabled if forced by the corresponding FrcEn bit in register RegClockCfg2. If Ck_Lo is selected by any of SelCkCR, SelCkPr1, SelCkPr2, its ReqCkLo signal becomes active and the oscillator as selected by the SelCkLo-multiplexer will be enabled, otherwise it shall be disabled. The oscillator is also enabled if forced by the corresponding FrcEn bit in register RegClockCfg2.
*
As such the oscillators are only active if there output clock is needed for either Ck_Hi or Ck_Lo. Alternatively the user may always force-on any RC oscillator and one of the external clock sources (Xtal, resonator, PC4 ext clock) Clock selection/request is provided as information which oscillator(s) are actually selected with its clock requested by a peripheral block. The request/selection bits CkSwSelX, CkSwSelHi, CkSwSelLo is high for the actual selected oscillator on the given clock switch. The coding is one-hot. Clock status information is provided to show which oscillator(s) are actually active and outputting their clock on their clock switch. The status bits CkSwStsX, CkSwStsHi, CkSwstsLo is high for the actual active oscillator on the given clock switch. The coding is one-hot. The clock selection and clock status signals are readable in register RegCkSw1 and RegCkSw2. The coding is onehot. A selected oscillator clock is only applied to the periphery if its selection and status bit match.
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9.4 OSCILLATORS CONTROL
The oscillator control block assures that only the oscillators which are requested or which are forced-on are really active. The various status signals allow close monitoring of the clock switching and give essential information for power saving. Figure 6; Oscillator control architecture Oscillator control architecture
trimOsc15M FrcEnRC15M SelRc15M EnDCDC trimOsc2M FrcEnRC2M SelRC2M FrcEnExtOsc SelExt PCInpE[4] SelCkExt= `11'
SelCkExt= `10' SelCkExt='01'
Cold start 4 pulses
Ck_15M
StsCSRC15M
RC_15M
StsEnRC15M Cold start 2 pulses
Ck_2M
StsCSRC2M
RC_2M
StsEnRC2M
EnExtPad StsEnReson StsEnXtal
PC4/OscOut
En Vreg En
En Cold start 16 pulses
Ck_PC4
StsCSPad
LF
HF
Cold start 4096 pulses
Ck_Reson
StsCSReson
PA4/OscIn
Cold start progammable 8k-32k pulses Cold start 32 pulses
Ck_Xtal32
StsCSXTAL
Sleep SCStart SCDis FrcEnRC8k SelRC8k WDDis
Ck_8k
StsCSRc8k
RC_8k
StsEnRC8k
Oscillator availability is delayed by an individual oscillator ColdStart delay. Each disabled oscillator or external clock will go through the ColdStart phase when enabled. Following delays apply: Oscillator RC 15 MHz RC 2MHz RC 8 kHz Ext: from Pad Ext: Resonator Ext: Xtal
ColdStart delay 4 pulses 2 pulses 32 pulses 16 pulses 4K pulses programmable by register bits XtalCldStart
The 32 KHz Xtal ColdStart delay is programmable by the register bits XtalCldStart as follows: RegXtalCldStart ColdStart delay 00 32K cycles (default) 01 24K cycles 10 16K cycles 11 8K cycles
The ColdStart functionality is blocking the given clock propagation to the circuit. The status of ColdStart function for each oscillator shall be readable by the register RegStsCStart bits StsCSReson, StsCSXtal, StsCSPad, StsCSRC8k, StsCSRC2M, StsCSRC15M.
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The oscillator Force-On functionality can be used to avoid recurrent coldstart delays on fast clock switching. An Oscillator is enabled if its clock is requested by either of the SelCkCR, SelCkPr1, SelCkPr2 clock selection bits or forced-on by register RegClockCfg2 bits FrcEnXXX as follows: Oscillator Condition Status bit RC15 MHz SelRC15M || FrcEnRC15M || EnDC-DC StsEnRC15M RC2 MHz SelRC2M || FrcEnRC2M StsEnRC2M Xtal (SelExt || FrcEnExt) && SelCkExt="01" StsEnXtal Resonator (SelExt || FrcEnExt) && SelCkExt="10" StsEnReson The oscillator enable signals are readable by the register RegStsEnOsc bits StsEnReson, StsEnXtal, StsEnRC8k, StsEnRC2M, StsEnRC15M. An External clock Source from pad PC4 is enabled if selected or forced-on by register RegClockCfg2 bit FrcEnExt , its status is read on StsCSPad: StsCSPad = (SelExt || FrcEnExt) && SelCkExt="11" PCInpE[4] must be high to allow PC4 clock input The RC 15 MHz oscillator is always automatically enabled if the DC-DC converter is switched on (register RegDCDCCfg bit EnDC-DC). The oscillators (except RC_8K) and the external clock sources are automatically disabled in Sleep mode. This has priority over Select and Force-On functionality. The oscillators and the external clock sources are automatically disabled by power-check functionality. This has priority over Select and Force-On functionality. The RC 8 kHz oscillator is enabled in Sleep mode with active sleepcounter function if the watchdog is enabled, if requested by any of the SelCkCR, SelCkPr1 and SelCkPr2 clock selection and when forced-on. The status bit of the RC_8k is readable in register RegStsEnOsc bit StsEnRC8k StsEnRC8k = FrcEnRC8k || SelRC8k || ((Sleep || SCStart) && !SCDis) || !WDDis Note: The RC_8kHz oscillator can only be disabled at least 300us after its coldstart. ( RegStsCStart.StsCSRC8k)
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9.5 CLOCK CONTROL REGISTERS
0x0000 Bits Name 7 SelSleep 6 SelPwrDwn 4 EnBrownOut 3:2 XtalCldStart 1 StdByFastWkUp 0 VSUPLow RegSysCfg1 Type ResVal RW 0 RW 0 RW 1 RW '00' RW 0 RO 0 ResSrc ResSys ResSys ResAna ResSys ResSys System Configuration - 1 Description Select Sleep mode on Halt Select Power-Down mode on Halt Enable Brown Out Select Xtal Osc. ColdStart length Stand-by mode fast Wakeup VSUP is Low - Tripler activated
0x0003 Bits Name 7:6 SelCkExt 5:4 SelCkHi 3:2 SelCkLo 1 0 FrcFastRead 0x0004 Bits Name 7 FrcEnRC15M 6 FrcEnRC2M 5 FrcEnRC8k 4 FrcEnExt 3:0 SelCkCR
RegClockCfg1 Type ResVal RW_Res '00' RW_Res '01' RW_Res '10' NI RW 0 RegClockCfg2 Type ResVal RW 0 RW 0 RW 0 RW 0 RW_Res 0x3
ResSrc ResSys ResSys ResSys ResSys
Clock Configuration - 1 Description Select External Component/Input clock source Select High freq. Clock source Select Low freq. Clock source Not implemented Force NVM Fast Read Clock Configuration - 2 Description Force 15 MHz RC Oscillator ON Force 2 MHz RC Oscillator ON Force 8 kHz RC Oscillator ON Force selected (SelCkExt) External Component/Input clock source ON Select CoolRisc/CPU Clock source Clock Configuration - 3 Description Select Prescaler1 Clock source Select Prescaler2 Clock source Ostcillators ColdStart Status Description ColdStart Status of (4 MHz) Resonator Oscillator ColdStart Status of (32K Hz) Xtal Oscillator ColdStart Status of External Pad-Clock ColdStart Status of 8 kHz RC Oscillator ColdStart Status of 2 MHz RC Oscillator ColdStart Status of 15 MHz RC Oscillator Ostcillators Enable Status Description Not implemented Enabled Status/State of (4 MHz) Resonator Oscillator Enabled Status/State of (32K Hz) Xtal Oscillator Enabled Status/State of 8 kHz RC Oscillator Enabled Status/State of 2 MHz RC Oscillator Enabled Status/State of 15 MHz RC Oscillator
ResSrc ResSys ResSys ResSys ResSys ResSys
0x0005 Bits Name 7:5 SelCkPr1 4:2 SelCkPr2 1:0 0x02A5 Bits Name 7:6 5 StsCSReson 4 StsCSXtal 3 StsCSPad 2 StsCSRC8k 1 StsCSRC2M 0 StsCSRC15M 0x02A6 Bits Name 7:5 4 StsEnReson 3 2 1 0 StsEnXtal StsEnRC8k StsEnRC2M StsEnRC15M
RegClockCfg3 Type ResVal RW_Res '011' RW_Res '100' NI RegStsCStart Type ResVal NI RO 1 RO 1 RO 1 RO 0 RO 0 RO 1 RegStsEnOsc Type ResVal NI RO 0 RO RO RO RO 0 1 1 0
ResSrc ResSys ResSys -
ResSrc ResSys ResSys ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys ResSys
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0x02A7 Bits Name 7 CkSwSelX RegCkSw1 Type ResVal RO 0 ResSrc ResSys Clock switches Selector/Request and current Status - 1 Description Ck_SW Clock (Ck-Hi/Ck-Lo) Sync. clock switch Selector/Request Status `1' - CK_Lo, `0' - CK_Hi Ck_SW Clock (Ck-Hi/Ck-Lo) Sync. clock switch current Status `1' - CK_Lo, `0' - CK_Hi Ck-Hi Clock switch (one-hot) Selector/Request Status bit0 - Ck_15M, Bit1 - Ck_2M, bit2 - Ck_Ext Ck-Hi Clock switch (one-hot) current Status bit0 - Ck_15M, Bit1 - Ck_2M, bit2 - Ck_Ext Clock switches Selector/Request and current Status - 2 Description Not implemented Ck-Lo Clock switch (one-hot) Selector/Request Status bit0 - Ck_Ext, Bit1 - Ck_Ext/4, bit2 - Ck_8k Ck-Lo Clock switch (one-hot) current Status bit0 - Ck_Ext, Bit1 - Ck_Ext/4, bit2 - Ck_8k
6
CkSwStsX
RO
0
ResSys
5:3 2:0
CkSwSelHi CkSwStsHi
RO RO
'010' '010'
ResSys ResSys
0x02A8 Bits Name 7:6 5:3 CkSwSelLo 2:0 CkSwStsLo
RegCkSw2 Type ResVal NI RO '100' RO '100'
ResSrc ResSys ResSys
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 10. PRESCALER1
The prescaler1 is a 15 stage clock divider. It is typically used to deliver the input clocks to the digital peripherals (timers, SPI, etc..). Its last stage output is on 1Hz (at 32768Hz input clock) and therefore most often used to construct a RTC (Real Time Clock) system. It can also be used as a free running counter by reading the current status of Pr1Ck0(MSB) to Pr1Ck7(LSB) in register RegPresc1Val.
10.1 PRESCALER1 CLOCK SELECTION
The Prescaler1 input clock Ck_Pr1 is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different prescaler1 clocking possibilities. The prescaler clock divider selection is done in register RegClockCfg3 bits SelCkPr1. SelCkPr1 Prescaler1 Clock 000 Ck_Hi (divided by 1) 001 Ck_Hi divided by 2 010 Ck_Hi divided by 4 Ck_Hi divided by 8 (default) 011 100 Ck_Lo (divided by 1) Others Ck_Hi divided by 8 The default Prescaler1 clock source after system reset (ResSys) shall be Ck_Hi divided by 8 (selection 0x3). It is possible to run the 15 stage precaler1 on 13 stages only. This is typically used when connecting the RC_8K oscillator as the prescaler1 clock source and allow to keep the nominal prescaler output frequencies as if there would be an 32kHz Xtal oscillator connected (prescaler at 15 stages). The prescaler1 length selection is done in register RegPrescCfg bit Presc1Len (`0'= 15 stages, `1'=13 stages). The Signals Pr1Ck14 and Pr1Ck13 are thus not influenced by the shortening. Assuming a Prescaler1 with N stages, then the signal Pr1Ck[N] is the input of the first stage, Pr1Ck[N-1] is the output of the first stage (input divided by 2) and Pr1Ck0 is the output of the last stage (the lowest frequency). This leads to following clock source name definitions. Prescaler1 Clock Name Presc1Len = `0' Presc1Len = `1' stage Division by Fout Division by Fout Prescaler source: 1 2^0 32K 1 2^0 8K Pr1Ck15 Stage 1 2 2^1 16K 2 2^1 4K Pr1Ck14 Stage 2 4 2^2 8K 4 2^2 2K Pr1Ck13 Stage 3 8 2^3 4K 2 2^1 4K Pr1Ck12 Stage 4 16 2^4 2K 4 2^2 2K Pr1Ck11 Stage 5 32 2^5 1K 8 2^3 1K Pr1Ck10 Stage 6 64 2^6 512 16 2^4 512 Pr1Ck9 Stage 7 128 2^7 256 32 2^5 256 Pr1Ck8 Stage 8 256 2^8 128 64 2^6 128 Pr1Ck7 Stage 9 512 2^9 64 128 2^7 64 Pr1Ck6 Stage 10 1K 2^10 32 256 2^8 32 Pr1Ck5 Stage 11 2K 2^11 16 512 2^9 16 Pr1Ck4 Stage 12 4K 2^12 8 1K 2^10 8 Pr1Ck3 Stage 13 8K 2^13 4 2K 2^11 4 Pr1Ck2 Stage 14 16K 2^14 2 4K 2^12 2 Pr1Ck1 Stage 15 32K 2^15 1 8K 2^13 1 Pr1Ck0 The frequencies Fout given in this table are based on 32 KHz clock selection as a prescaler1 input source.
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10.2 PRESCALER1 RESET
Writing `1' to the bit Presc1Clr in register RegPrescCfg sets all stages to `1' and counting restarts. 10.2.1.1 PRESCALER1 INTERRUPT GENERATION The prescaler1 generates 2 interrupt signals * IntPr1Ck0 interrupt signal is generated on the stage 15 overrun (rising Pr1Ck0 edge) * IntPr1Ck5/3 interrupt signal is generated on the stage 10 or stage12 overrun (rising Pr1Ck3 or Pr1Ck5 edge). The selection is done in register PrescCfg bit Presc1SelIntck5/3 as follows: Presc1SelIntck5/3 Int. Freq. (based on 32KHz) Pr1-Ck 0 (Default) 8 Hz Pr1Ck3 1 32 Hz Pr1Ck5 The frequencies given in this table are based on 32 KHz clock selection as a prescaler1 input source.
10.3 PRESCALER REGISTERS
0x0007 Bits Name 7 Presc1Clr 6 Presc1Len 5 Presc1SelIntck5/3 4 Presc2Clr 3:0 0x0008 Bits Name 7:0 Presc1Val RegPrescCfg Type ResVal OS 0 RW 0 RW 0 OS 0 NI RegPresc1Val Type ResVal RO 0xFF ResSrc ResSys ResSys Prescaler-1/2 Configuration Description Prescaler-1 Clear counter Prescaler-1 Length Select Prescaler-1 irq-B source: 0-8Hz, 1-32Hz Prescaler-2 Clear counter Not implemented Prescaler-1 Value (MSB) Description Prescaler-1 Value (MSB) , Pr1Ck0 to Pr1Ck7 status
ResSrc ResSys
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 11. PRESCALER2
The prescaler2 is a 10 stage clock divider. It is typically used to deliver the input clocks to the digital peripherals (timers, SPI, etc. It can also be used as a free running counter by reading the current status of Pr2Ck0(MSB) to Pr2Ck7(LSB) in register RegPresc2Val.
11.1 PRESCALER2 CLOCK SELECTION
The Prescaler2 input clock Ck_Pr2 is derived from divided or undivided Ck_Hi or Ck_Lo input clock. Below table is an overview of the different prescaler1 clocking possibilities. The prescaler clock divider selection is done in register RegClockCfg3 bits SelCkPr2. SelCkPr2 Prescaler2 Clock 000 Ck_Hi (divided by 1) 001 Ck_Hi divided by 2 010 Ck_Hi divided by 4 011 Ck_Hi divided by 8 100 Ck_Lo (divided by 1) Others Ck_Lo (divided by 1) The default Prescaler-2 clock source after system reset (res_sys) shall be Ck_Lo divided by 1 (selection 0x4). Assuming a Prescaler2 with N stages, then the signal Pr2ck[N] is the input of the first stage, Pr2Ck[N-1] is the output of the first stage (input divided by 2) and Pr2Ck0 is the output of the last stage (the lowest frequency). This leads to following clock source name definitions. Prescaler2 Clock Name Division by Fout stage Prescaler source: 1 2^0 2M Pr2Ck10 Stage 1 2 2^1 1M Pr2Ck9 Stage 2 4 2^2 500 k Pr2Ck8 Stage 3 8 2^3 250 k Pr2Ck7 Stage 4 16 2^4 125 k Pr2Ck6 Stage 5 32 2^5 62500 Pr2Ck5 Stage 6 64 2^6 31250 Pr2Ck4 Stage 7 128 2^7 15625 Pr2Ck3 Stage 8 256 2^8 7812.5 Pr2Ck2 Stage 9 512 2^9 3906.25 Pr2Ck1 Stage 10 1K 2^10 1953.125 Pr2Ck0 The frequencies Fout given in this table are based on 32 KHz clock selection as a prescaler2 input source.
11.2 PRESCALER2 RESET
Writing `1' to the bit Presc2Clr in register RegPrescCfg sets all stages to `1' and counting restarts.
11.3 PRESCALER2 REGISTERS
0x0007 Bits Name 7 Presc1Clr 6 Presc1Len 5 Presc1SelIntck5/3 4 Presc2Clr 3:0 0x0009 Bits Name 7:0 Presc2Val RegPrescCfg Type ResVal OS 0 RW 0 RW 0 OS 0 NI RegPresc2Val Type ResVal RO 0xFF ResSrc ResSys ResSys Prescaler-1/2 Configuration Description Prescaler-1 Clear counter Prescaler-1 Length Select Prescaler-1 irq-B source: 0-8Hz, 1-32Hz Prescaler-2 Clear counter Not implemented Prescaler-2 Value (MSB) Description Prescaler-2 Value (MSB), Pr2Ck0 to Pr2Ck7 status
ResSrc ResSys
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 12. INTERRUPT AND EVENT CONTROLLER
12.1 INTERRUPTS GENERAL
12.1.1 BASIC FEATURES
The circuit handles 24 independent Interrupt sources grouped into 3 priority levels. * Highest Priority : Level 0 : Prescaler1, PmMiss, GASP, ADC, Timer, Ports * Medium Priority : Level 1 : SPI, Prescaler1, OpAmp, Timer, Ports * Lowest Priority : Level 2 : Timer, Ports, Sleep counter, VLD As such the circuit contains * 13 external Interrupts (Ports, SPI, OpAmp, VLD, GASP) * 12 internal Interrupts (Prescaler, DoC, Timer, SPI, PmMiss, Sleep Counter) Interrupt from SPI and Timer may be initialized by either external or internal actions (i.e. timer running on external clock) Interrupts force a CALL to a fixed interrupt vector, save the program counter (PC) onto the hardware stack and reset the general interrupt bit (GIE). If the CPU was in StandBy mode prior to Interrupt then it will come back in active mode. Each priority level has its own interrupt vector. * Level 1 sets bit IN1 in CoolRISC status register Program memory address 1 Call Vector 1 * Level 2 sets bit IN2 in CoolRISC status register Program memory address 2 Call Vector 2 * Level 0 sets bit IN0 in CoolRISC status register Program memory address 3 Call Vector 0 The GIE bit is restored when returning from interrupt with the RETI instruction. The RET instruction does not reinstall the GIE. Nested interrupts are possible by re-enabling the GIE bit within the interrupt routine. Functions such as interrupt Pre- or Post-masking, enabling and clearing are available on different levels in the interrupt structure. At power up or after any reset all interrupt inputs are masked and the GIE is cleared. The Interrupt handling is split into 2 parts. * One part deals with the acquisition, masking and clearing of the interrupts outside of the CPU. Interrupt acquisition, IRQ Controller nd * The 2 part covers all aspects of priority and interrupts enabling inside the CoolRISC core. CPU interrupts handling Figure 7, Interrupt top level diagram
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12.2 INTERRUPT ACQUISITION
A positive edge on any of the unmasked interrupt source signals will set the corresponding interrupt register bit and activate the mapped CPU interrupt input. (I.e. Timer3 interrupt IntTim3 will set bit Int1StsTim3 in register RegInt1Sts and activate the CPUInt1 interrupt input if mask bit Int1MskTim3 is `1' [non-masked] ). The 3 priority branches for interrupt acquisition are totally independent of each other, masking and selective clear of interrupts on one interrupt vector input does not modify the others. All Interrupts inputs are available in active and standby mode. Table 1. Interrupts signal sources and destination
Interrupt sources IntPort0 IntTim1 IntPr1Ck0 IntADC IntDoCDM IntDoCPM IntGASP IntPmMiss IntPort2 IntPort1 IntTim2 IntTim3 IntOpAmp IntPr1Ck5/3 IntSPIStop IntSPIStart IntVLD IntSlpCnt IntPort7 IntPort6 IntPort5 IntPort4 IntPort3 IntTim4 Int Mapping vector Int0StsPort0 Int0StsTim1 Int0StsPrCk0 Int0StsADC 0 Int0StsDoCDM Int0StsDoCPM Int0StsGASP Int0StsPmMiss Int1StsPort2 Int1StsPort2 Int1StsTim2 Int1StsTim3 1 Int1StsOpAmp Int1StsPr1Ck5/3 Int1StsSPIStop Int1StsSPIStart Int2StsVLD Int2StsSlpCnt Int2StsPort7 Int2StsPort6 2 Int2StsPort5 Int2StsPort4 Int2StsPort3 Int2StsTim4 remark PA0 or PC0, positive and/or negative edge Timer1 Input capture, Compare value, Compare Full Prescaler1 1Hz (Pr1Ck0) ADC conversion finished DoC data memory address match DoC program memory address match GASP data reception with sign='1' Program memory, wait introduction PA2 or PC2, positive and/or negative edge PA1 or PC1, positive and/or negative edge Timer2, Input capture, Compare value, Compare Full Timer3, Input capture, Compare value, Compare Full Comparator; falling and/or rising output change Prescaler 1, 8Hz or 32Hz (falling edge) SPI, Stop transmission 1 byte SPI, Start transmission 1byte Voltage level detector; input low Sleep counter wakeup timeout PA7 or PC7, positive and/or negative edge PA6 or PC6, positive and/or negative edge PA5 or PC5, positive and/or negative edge PA4 or PC4, positive and/or negative edge PA3 or PC3, positive and/or negative edge Timer4, Input capture, Compare value, Compare Full Sleep wakeup X (PA)
X X (PA) X (PA)
X
X X X (PA) X (PA) X (PA) X (PA) X (PA)
The following interrupt sources can wake-up the device from the Sleep mode if enabled by appropriate interrupt masks: Table 2. Wake-Up Interrupts Interrupt Source
Interrupt Status
IntXStsPort7 to IntXStsPort0 PortA; regardless of RegIntPortSrc Int2StsSlpCnt Sleep counter SVLD Int2StsVLD OpAmp Int1StsOpAmp GASP Int0StsGASP Direct (non-debounced) port A interrupts are, used for the wake-up, totaly independent of the debouncer settings.
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12.3 INTERRUPTS FROM IO PORTS
The register RegIntPortSrc selects the port interrupt source IntPort coming from port A or port C in Active and StandBy modes. In Sleep mode, the port A is always selected independent of RegIntPortSrc settings. * If RegIntPortSrc[X] = `0' then IntPort[X] source shall be IntPA[X] otherwise it is IntPC[X]. * The default value of RegIntPortSrc is 0x00, i.e. IntPA[X] is selected.
12.4 INTERRUPT ACQUISITION MASKING.
At start up or after any reset all interrupt sources are masked (mask bits are `0'). To activate a specific interrupt source input the corresponding mask bit must be set `1'. Masking does not clear an existing interrupt but will prevent future interrupts on the same input. Refer to Figure 8, Interrupt acquisition architecture.
12.4.1 PRE AND POSTMASKING OF INTERRUPTS
One pair of registers for each level of priority RegIntXMsk and RegIntXPostMsk control the interrupt generation for CPU and catch an incoming request into the status registers RegIntXSts as follows: * If RegIntXMsk[Y] ='1' then the appropriate CPU interrupt line IntX is asserted and interrupt is caught in the status register RegIntXSts[Y]. * If RegIntXMsk[Y] ='0' then the appropriate CPU interrupt line IntX is NOT asserted. The interrupt request is caught in the status register RegIntXSts[Y] only if RegIntXPostMsk[Y] ='1'. * If RegIntXMsk[Y] ='0' then the appropriate CPU interrupt line IntX is NOT asserted. The interrupt request is NOT caught in the status register RegIntXSts[Y] if RegIntXPostMsk[Y] ='0'. Figure 8, Interrupt acquisition architecture
Interrupt aquisition
SW write `1' to IntXSts bit IntXMsk IntXPostMask D Q
IntX IntXSts
D Q To Databus
IntXSource
Ck
SW read RegIntXSts
En
INV SW write `1' to IntXSts bit
IntPort0 IntTim1 IntPr1Ck0 IntADC IntDoCDM IntDocPM IntGASP IntPmMiss IntPort2 IntPort1 IntTim2 IntTim3 IntOpAmp IntPr1Ck5/3 IntSPIStop IntSPIStart IntVLD IntSlpCnt IntPort7 IntPort6 IntPort5 IntPort4 IntPort3 IntTim4
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Int0Msk 8 Int0PostMsk Int0Source 8
CLR
8
Q
Int0[8:0] CPUInt0
D
SET
Int0Sts[8:0]
Q
8
Int1Msk Int1PostMsk Int1Source 8
CLR
8 8
D
SET
Int1[8:0] CPUInt1
Q
Int1STS[8:0]
Q
8
Int2Msk 8 Int2PostMsk Int2Source 8
CLR
8
Q
Int2[8:0] CPUInt2
D
SET
Int2STS[8:0]
Q
8
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12.5 INTERRUPT ACQUISITION CLEARING
A pending interrupt can be cleared in 3 ways * Reading the interrupt registers RegInt0Sts, RegInt1Sts and RegInt2Sts will automatically clear all stored interrupts which were set prior to the read in the corresponding register. This read is normally done inside the interrupt subroutine to determine the source of the interrupt. * Each interrupt request status bit can be individually cleared (set `0') by writing `0' to the corresponding RegInt0Sts, RegInt1Sts and RegInt2Sts register bit. Software clearing of the interrupt status bit has priority over an incoming interrupt. * At power up or after any reset all interrupt registers are reset.
12.5.1 SOFTWARE INTERRUPT ACQUISITION SET
Each interrupt request status bit can be individually set (set `1') by writing `1' to the corresponding RegInt0Sts, RegInt1Sts and RegInt2Sts register bit. Write `1' has the highest priority on the status bit.
12.6 INTERRUPT REGISTERS
0x0061 Bits Name 7 Int0StsPort(0) 6 Int0StsTim1 5 Int0StsPr1Ck0 4 Int0StsADC 3 Int0StsDoCDM 2 Int0StsDoCPM 1 Int0StsGASP 0 Int0StsPmMiss 0x0062 Bits Name 7 Int1StsPort(2) 6 Int1StsPort(1) 5 Int1StsTim2 4 Int1StsTim3 3 Int1StsOpAmp 2 Int1StsPr1Ck5/3 1 Int1StsSPIStop 0 Int1StsSPIStart 0x0063 Bits Name 7 Int2StsVLD 6 Int2StsSlpCnt 5 Int2StsPort(7) 4 Int2StsPort(6) 3 Int2StsPort(5) 2 Int2StsPort(4) 1 Int2StsPort(3) 0 Int2StsTim4 RegInt0Sts Type ResVal RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RegInt1Sts Type ResVal RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RegInt2Sts Type ResVal RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 RW-INT 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-0 Status Description Interrupt level-0 Status - Port(0) Interrupt level-0 Status - Timer-1 Interrupt level-0 Status - Prescaler1 Ck0 (1Hz) Interrupt level-0 Status - ADC Interrupt level-0 Status - DoC DM Interrupt level-0 Status - DoC PM Interrupt level-0 Status - GASP Interrupt level-0 Status - PM_Miss Interrupt level-1 Status Description Interrupt level-1 Status - Port(2) Interrupt level-1 Status - Port(1) Interrupt level-1 Status - Timer-2 Interrupt level-1 Status - Timer-3 Interrupt level-1 Status - OpAmp Interrupt level-1 Status - Prescaler1 Ck5 or Ck3 Interrupt level-1 Status - SPI_Stop Interrupt level-1 Status - SPI_Start Interrupt level-2 Status Description Interrupt level-2 Status - VLD Interrupt level-2 Status - Sleep Counter Interrupt level-2 Status - Port(7) Interrupt level-2 Status - Port(6) Interrupt level-2 Status - Port(5) Interrupt level-2 Status - Port(4) Interrupt level-2 Status - Port(3) Interrupt level-2 Status - Timer-4
ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
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0x0064 Bits Name 7 Int0MskPort(0) 6 Int0MskTim1 5 Int0MskPr1Ck0 4 Int0MskADC 3 Int0MskDoCDM 2 Int0MskDoCPM 1 Int0MskGASP 0 Int0MskPmMiss 0x0065 Bits Name 7 Int1MskPort(2) 6 Int1MskPort(1) 5 Int1MskTim2 4 Int1MskTim3 3 Int1MskOpAmp 2 Int1MskPr1Ck5/3 1 Int1MskSPIStop 0 Int1MskSPIStart 0x0066 Bits Name 7 Int2MskVLD 6 Int2MskSlpCnt 5 Int2MskPort(7) 4 Int2MskPort(6) 3 Int2MskPort(5) 2 Int2MskPort(4) 1 Int2MskPort(3) 0 Int2MskTim4 0x0067 Bits Name 7 Int0PostMskPort(0) 6 Int0PostMskTim1 5 Int0PostMskPr1Ck0 4 Int0PostMskADC 3 Int0PostMskDoCDM 2 Int0PostMskDoCPM 1 Int0PostMskGASP 0 Int0PostMskPmMiss 0x0068 Bits Name 7 Int1PostMskPort(2) 6 Int1PostMskPort(1) 5 Int1PostMskTim2 4 Int1PostMskTim3 3 Int1PostMskOpAmp 2 Int1PostMskPr1Ck5/3 1 Int1PostMskSPIStop 0 Int1PostMskSPIStart RegInt0Msk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RegInt1Msk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RegInt2Msk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RegInt0PostMsk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RegInt1PostMsk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-0 Mask Description Interrupt level-0 Mask - Port(0) Interrupt level-0 Mask - Timer-1 Interrupt level-0 Mask - Prescaler1 1Hz Interrupt level-0 Mask - ADC Interrupt level-0 Mask - DoC DM Interrupt level-0 Mask - DoC PM Interrupt level-0 Mask - GASP Interrupt level-0 Mask - PM_Miss Interrupt level-1 Mask Description Interrupt level-1 Mask - Port(2) Interrupt level-1 Mask - Port(1) Interrupt level-1 Mask - Timer-2 Interrupt level-1 Mask - Timer-3 Interrupt level-1 Mask - OpAmp Interrupt level-1 Mask - Prescaler1 Ck5 or Ck3 Interrupt level-1 Mask - SPI_Stop Interrupt level-1 Mask - SPI_Start Interrupt level-2 Mask Description Interrupt level-2 Mask - VLD Interrupt level-2 Mask - Sleep Counter Interrupt level-2 Mask - Port(7) Interrupt level-2 Mask - Port(6) Interrupt level-2 Mask - Port(5) Interrupt level-2 Mask - Port(4) Interrupt level-2 Mask - Port(3) Interrupt level-2 Mask - Timer-4 Interrupt level-0 Post_Mask Description Interrupt level-0 Post_Mask - Port(0) Interrupt level-0 Post_Mask - Timer-1 Interrupt level-0 Post_Mask - Prescaler1 1Hz Interrupt level-0 Post_Mask - ADC Interrupt level-0 Post_Mask - DoC DM Interrupt level-0 Post_Mask - DoC PM Interrupt level-0 Post_Mask - GASP Interrupt level-0 Post_Mask - PM_Miss Interrupt level-1 Post_Mask Description Interrupt level-1 Post_Mask - Port(2) Interrupt level-1 Post_Mask - Port(1) Interrupt level-1 Post_Mask - Timer-2 Interrupt level-1 Post_Mask - Timer-3 Interrupt level-1 Post_Mask - OpAmp Interrupt level-1 Post_Mask - Prescaler1 Ck5 or Ck3 Interrupt level-1 Post_Mask - SPI_Stop Interrupt level-1 Post_Mask - SPI_Start
ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
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0x0069 Bits Name 7 Int2PostMskVLD 6 Int2PostMskSlpCnt 5 Int2PostMskPort(7) 4 Int2PostMskPort(6) 3 Int2PostMskPort(5) 2 Int2PostMskPort(4) 1 Int2PostMskPort(3) 0 Int2PostMskTim4 0x006A Bits Name 7:0 IntPortSrc RegInt2PostMsk Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RegIntPortSrc Type ResVal RW 0x00 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Interrupt level-2 Post_Mask Description Interrupt level-2 Post_Mask - VLD Interrupt level-2 Post_Mask - Sleep Counter Interrupt level-2 Post_Mask - Port(7) Interrupt level-2 Post_Mask - Port(6) Interrupt level-2 Post_Mask - Port(5) Interrupt level-2 Post_Mask - Port(4) Interrupt level-2 Post_Mask - Port(3) Interrupt level-2 Post_Mask - Timer-4 Port Interrupt source selector: 0-PortA, 1-PortC Description Port Interrupt source selector: 0-PortA, 1-PortC
ResSrc ResSys
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12.7 EVENT GENERAL
12.7.1 BASIC FEATURES
Events are most commonly used to restart the processor from the StandBy mode without jumping to the interrupt vector. Events can also be combined with the JEV instruction (Jump on Event) or been used for wake-up from Sleep mode. The circuit handles 4 independent event sources grouped into 2 event sources, both of same priority * Bank 0 Source : EV0: GASP * Bank 1 Source : EV1: ADC, SPI, Sleep Counter Figure 9, Event top level diagram
Event Diagram
Bank 0 Event sources Bank 1 Event sources CPUEvt0 1 CPUEvt1 Event Controller 3 Event acquisition R/W Control RegEvtSts CPU CR816 Interrupt handling EV0 EV1
12.8 EVENT ACQUISITION
A positive edge on any of the unmasked event source signals will set the corresponding event status bit and activate the mapped CPU event input. (I.e. ADC event EvtADC will set bit Evt1StsADC in register RegEvtSts and activate the CPUEvt1 event input if mask bit Evt1MskADC is `1' [non-masked] ). The 2 branches for event acquisition are totally independent of each other, masking and selective clear of events on one event status input does not modify the others. Table 3. Event signal sources and destination
Event sources EvtGASP EvtSlpCnt EvtSPI EvtADC Event Mapping bank 0 Evt0StsGASP Evt1StsSlpCnt 1 Evt1StsSPI Evt1StsADC remark GASP data reception Sleep counter wakeup timeout SPI, Start or Stop transmission ADC conversion finished Sleep wakeup X X
The following event sources shall wake-up the device from the Sleep mode if enabled by appropriate event masks: Table 4. Wake-Up Events
Event Source Sleep counter GASP Evt1StsSlpCnt Evt0StsGASP Event Status
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12.9 EVENT MASKING
At start up or after any reset all event sources are masked (mask bits are `0'). To activate a specific event source input the corresponding mask bit must be set `1'. Masking does not clear an existing event but will prevent future events on the same input. Refer to Figure 10, Event acquisition architecture. PRE AND POSTMASKING OF EVENTS 12.9.1.1 One pair of registers bits for each event EvtXMsk and EvtXPostMsk in register RegEvtCfg control the event generation for CPU and catch an incoming request into the status registers RegEvtSts as follows: * If EvtXMsk='1' then the appropriate CPU event line EVX is asserted and the event is caught in the status bit EvtXSts. * If EvtXMsk='0' then the appropriate CPU interrupt line EVX is NOT asserted. The event is caught in the status register EvtXSts only if EvtXPostMsk='1'. * If EvtXMsk='0' then the appropriate CPU interrupt line EVX is NOT asserted. The event is NOT caught in the status register EvtXSts only if EvtXPostMsk='0'. Figure 10, Event acquisition architecture
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12.10
EVENT ACQUISITION CLEARING
A pending event can be cleared in 3 ways 1. Reading the event register RegEvtSts will automatically clear all stored events which were set prior to the read in the corresponding register. 2. Each event status bit can be individually cleared (set `0') by writing `0' to the corresponding EvtXSts bit. At power up or after any reset all event registers bits are reset.
12.11
SOFTWARE EVENT SETTING
Each event status bit can be individually set (set `1') by writing `1' to the corresponding EvtXSts bit in register RegEvtCfg.
12.12
EVENT REGISTERS
RegEvtSts Type NI RW-INT RW-INT RW-INT RW-INT ResVal 0 0 0 0 ResSrc ResSys ResSys ResSys ResSys Event Status Description Not implemented Event level-1 Status - Sleep Counter Event level-1 Status - SPI Event level-1 Status - ADC Event level-0 Status - GASP Event Configuration Description Event level-1 Post-Mask - Sleep Counter Event level-1 Mask - Sleep Counter Event level-1 Post-Mask - SPI Event level-1 Mask - SPI Event level-1 Post-Mask - ADC Event level-1 Mask - ADC Event level-0 Post-Mask - GASP Event level-0 Mask - GASP
0x006B Bits Name 7:4 3 Evt1StsSlpCnt 2 Evt1StsSPI 1 Evt1StsADC 0 Evt0StsGASP 0x006C Bits Name 7 Evt1PostMskSC 6 Evt1MskSC 5 Evt1PostMskSPI 4 Evt1MskSPI 3 Evt1PostMskADC 2 Evt1MskADC 1 Evt0PostMskGasp 0 Evt0MskGasp
RegEvtCfg Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0
ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 13. CPU INTERRUPT AND EVENT HANDLING
The CPU has three interrupt inputs of different priority. These inputs are directly connected to the peripheral interrupt acquisition block. Each of these inputs has its own interrupt vector. Individual interrupt enabling mechanism is provided for the 2 low priority inputs (IE1, IE2). The GIE acts as a master enable, if GIE is cleared no interrupt can reach the CPU, but may still be stored in the interrupt acquisition block. If the hardware stack of the CPU is full, all interrupt inputs are blocked. The number of implemented hardware stack levels is 5 but If CPU HW stack level is on level 4, only IntGASP, IntDoCPM and IntDoCDM shall generate a CPU interrupt. Figure 11, CPU Interrupt architecture and Status register shows the architectural details concerning the interrupt and event latching and its enabling mechanism. Figure 11, CPU Interrupt architecture and Status register block
5 5 EV1 EV0 IN0 Status_e interrupt and envent latch Status_in[4:0] 1 5 0 ck1 5 CPUInt0 CPUInt1 CPUInt2 CPUEvent0 ck3 IE2 IN2 IE1 IN1
(=DebWakeUp) (CPUEvent1=VSS)
GIE HW stack not full MSB IE2 IE1 Mask
CPU Status register
GIE IN2 IN1 IRQ status IN0 EV1
LSB EV2
Event status
An interrupt from the peripheral acquisition block i.e. CPUInt2 is synchronized in the CPU interrupt latch and fed to the CPU interrupt handler signal IN2 if enable bits IE2 and GIE are set and the hardware stack is not full. Same thing applies to CPUInt1. CPUint0 is maskable only with GIE. As soon as the interrupt is latched, the GIE bit will be automatically cleared to avoid interleaved interrupts. Reading the interrupt acquisition register will clear the pending interrupt and at the end of the interrupt routine the RETI instruction will reinstall the GIE bit. The CPU will loop in the interrupt routine as long as there is a CPU interrupt input active and the corresponding IE1, IE2 and GIE are set. Refer to 12.5 for Interrupt acquisition Clearing. An interrupt or Event will also clear the CPU Halt mode. The HALT mode disabling remains active as long as one of the EV0, EV1, IN0, IN1, and IN2 signals is set. Before leaving the interrupt service routine one needs to clear the active IRQ acquisition bit (inside RegIntxx) and the corresponding status bit (IN0, IN1, and IN2) in the CoolRISC status register. Failure to do so will re-invoke the interrupt service routine just after the preceding RETI instruction. Software Interrupts and Events The above shown CPU Interrupt handling implementation is an extension to the base structure and as such allows software interrupts and software events to be written directly in the interrupt and event latches (write `1' to CPU status register bit 0 to 4, signals status_e and status_in). Software written interrupts and events remain stored in the interrupt latch until they get cleared again (write `0' to status register bit 0 to bit 4).
13.1 INTERRUPT PRIORITY
Interrupt priority is used only to select which interrupt will be processed when multiple interrupt requests occur simultaneously. In such case the higher priority interrupt is handled first. At the end of the interrupt routine RETI the processor will immediately go back into the interrupt routine to handle the next interrupt of highest priority. If a high priority interrupt occurs while the CPU is treating a low priority interrupt, the pending interrupt must wait until the GIE is enabled, usually by the RETI instruction.
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13.2 CPU STATUS REGISTER
The status register, used to control the interrupts and events, is an internal register to the CoolRISC CPU. It therefore does not figure in the peripheral memory mapping. All CPU enable bits for the interrupts and the current status of the events and the interrupts are part of this register. Table 5. CPU status register description Reset by R/W Description ResSys ResSys ResSys ResSys R/W R/W R/W* R/W Level 2 Interrupt enable `1' = enabled, `0' = disabled Level 1 Interrupt enable `1' = enabled, `0' = disabled General interrupt enable `1' = enabled, `0' = disabled Interrupt request level 2 flag, shows CPUInt2 `1' = IRQ pending, `0' = no IRQ The IRQ may only take place if IN2, IE2, and GIE are set Interrupt request level 1 flag, shows CPUInt1 `1' = IRQ pending, `0' = no IRQ The IRQ may only take place if IN1, IE1, and GIE are set Interrupt request level 0 flag, shows CPUInt1 `1' = IRQ pending, `0' = no IRQ The IRQ may only take place if IN0 and GIE are set Event request 1
Bit 7 6 5 4
Name IE2 IE1 GIE IN2
Reset 0 0 0 0
3
IN1
0
ResSys
R/W
2
IN0
0
ResSys
R/W
1
EV1
0
ResSys
R/W
0 EV0 0 ResSys R/W Event request 0 *Clear General Interrupt Enable bit GIE. Special care must be taken clearing the GIE bit. If an interrupt arrives during the clear operation the software may still branch into the interrupt routine and will set the GIE bit by the interrupt routine ending RETI instruction. This behavior may prevent from creating 'interrupt protected' areas within your code. A suitable workaround is to check if the GIE clearing took effect (Instruction) TSTB before executing the protected section.
13.3 CPU STATUS REGISTER PIPELINE EXCEPTION
Another consequence of the above interrupt implementation is that several instruction sequences work in a different way than expected. These instructions are mostly related to interrupt and event signals. For `normal' instructions the pipeline is completely transparent. If an interrupt is set by software (i.e. write into the status register with a MOVE stat) the pipeline causes the next instruction to be executed before the processor jumps to the interrupt subroutine. This allows one to supply a parameter to a `trap' as in Code shown below. SETB stat, MOVE a #4 #parameter ; trap ;
If an event bit is set by software (i.e. write into the CPU status register with a MOVE stat) and if a JEV (jump on event) instruction immediately follows the move, the jump on event will act as if the move has not been executed, since the write into the CPU status register will occur only once the JEV has been executed. The move takes 3 cycles to be executed and the JEV only one.
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13.4 PROCESSOR VECTOR TABLE
Address 1, 2 and 3 of the program memory are reserved for interrupt subroutine calls. Generally the first four addresses of the program memory are reserved for the processor vector table. The address 0 of the program memory contains the jump to the start-up routine Table 6. Processor vector table Address Accessed by 0 ResSys 1 IN1 2 IN2 3 IN3
Description Any reset, start-up address Interrupt level 1 Interrupt level 2 Interrupt level 0
Priority Maximal, above interrupts medium low high
13.5 CONTEXT SAVING
Since an interrupt may occur any time during normal program execution, there is no way to know which processor registers are used by the user program. For this reason, all resources modified in the interrupt service routine have to be saved upon entering and restored when leaving the service routine. The flags(C, V) and the accumulator (A) must always be saved, since most instructions will modify them. Other registers need only to be saved when they are modified in the interrupt service routine. There is a particular way to follow when saving resources. The accumulator should be saved first, followed by the flags and then the other registers
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 14. PORT A
The port A is general purpose 8-bit input output port. Each of the 8 Port A terminals can be configured to receive either Analog or digital Input or drive out analog or digital data.
14.1 PORT A TERMINAL MAPPING
Several digital and analog functions are mapped on the port A terminals. Please refer also to the concerned chapters. Table 14.1-1 Port A terminal mapping
Reset & WkUp Timer clock Timer start PWM output FrqOut strength sig sig sig sig sig sig Vref_out VLD VLD SCLK SOUT sig sig HD HD HD HD
Name PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
IRQ
ADC
VREF
VLD
OPAMP
SPI
CLOCK
PAIRQ0 ADC0 Rst_Wkup0 PAIRQ1 ADC2 Rst_Wkup1 PAIRQ2 ADC4 Rst_Wkup2 Vref_ADC PAIRQ3 ADC6 Rst_Wkup3 PAIRQ4 PAIRQ5 PAIRQ6 PAIRQ7 Rst_Wkup4 Rst_Wkup5 Rst_Wkup6 Rst_Wkup7 VLD OPA_Out SIN SOUT
t1ck0_in start1_in t2ck0_in start2_in t3ck0_in start4_in t4ck0_in start5_in SIN XIN
VLD OPA_INM OPA_INP
Note: on all bit of port A debouncers are enable by default after reset.
14.2 PORT A IO OPERATION
All IO modes are individually selectable for each port A terminal. Refer to table below. Table 14.2-1 Port A IO selections PA[n] Output data PA[n] Terminal
PAInpE[n]
PAOE [n]
PAOD[n]
PAPU[n]
Analog signal connection (in out) Analog signal connection (in out) with weak load to VDD or VSS Input mode Input mode with pull-up Input mode with pull-down Output, CMOS high level drive Output, CMOS low level drive Output, open drain, high-Z Output, open drain with pull-up Output, open drain low level drive
0 0 0 0 0 0 1 1 1 1 1
X X X X X X 1 0 1 1 0
X X X X X X 0 0 1 1 1
0 1 0 0 1 0 X X 0 1 X
0 X 1 0 X 1 X X X X X
PAPD[n]
Modes
Notes
0 0 0 1 1 1 X X X X X
High-Z RLoad to VDD RLoad to VSS High-Z Weak Hi Weak Lo 1 0 High-Z Weak Hi 0
Digital input is blocked, Analog functions can be connected CPU reads `0' Digital input, no-pull, needs external driver Digital input with pullup Digital input with pulldown Pull resistors disabled Pull resistors disabled Pull-down disabled, Usually ext Resistor pull-up Pull-up active Pull-up disabled
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Figure 12; Port A IO configuration
* * * * *
For maximum flexibility all Port A configuration bits are are fully user configurable. The pull resistors are only active if the pad driver is not driving the pad terminal, and pullup or pulldown resistors are enabled. Pullup has priority over pulldown. The CPU read of the port A terminal logic value (PA[n]) in register RegPADIn is depending of the PAInpEn blocking bit. As such one reads `0' if PAInpEn='0' (Input blocked) and the terminal logic value if PAInpEn='1'. At power-up, the PA[n] terminals are tristate with pullup and pulldown resistors disconnected and the input is disabled. As such all PA terminal can float without the penalty of additional power consumption. All PA input signal sources for Timer, SPI, PA-Reset, PA-IRQ are coming from the debouncer output PADeb[n].
Note: Make sure to setup the terminal correctly before using it as either digital IO or as an analog connection.
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14.3 OUTPUT SIGNALS ON PORT A
Different internal clock frequencies and PWM signals can be outout on all port A terminals. (PA[n] Output data) * The selection is done with the registers PA[n]OutSel1,0 . All clock outputs (PR1_x, PR2_x) have a 50% duty cycle. The Clock outputs CK_x have a duty cycle corresponding to the duty cycle of their clock source. * By default the register data PADOut[n] value is seleted as data output. * Data is only output if the corresponding PAOutEn[n] bit is high. Table 14.3-1 Port AOutput signal selection PA0OutSel1 PA0OutSel0 PA0 Output Data remarks 0 0 PADOut[0] 0 1 PWM3_N 1 0 PWM2_N 1 1 PWM4_N PA1OutSel1 PA1OutSel0 PA1 Output Data remarks 0 0 PADOut[1] 0 1 Pr1Ck11 2kHz if CK_PR1=32kHz 1 0 PWM1 1 1 PWM2_N PA2OutSel1 PA2OutSel0 PA2 Output Data remarks 0 0 PADOut[2] 0 1 SOUT 1 0 PWM1 1 1 Ck_Hi PA3OutSel1 PA3OutSel0 PA3 Output Data remarks 0 0 PADOut[3] 0 1 Ck_Lo 1 0 Pr1Ck11 2kHz if CK_PR1=32kHz 1 1 Pr1Ck10 1kHz if CK_PR1=32kHz PA4OutSel1 PA4OutSel0 PA4 Output Data remarks 0 0 PA-DOut[4] 0 1 Ck_Hi_N 1 0 Pr2Ck6_N 125kHz if CK_PR2=2MHz 1 1 Pr2Ck4_N 31kHz if CK_PR2=2MHz PA5OutSel1 PA5OutSel0 PA5 Output Data remarks 0 0 PADOut[5] 0 1 PWM3 1 0 PWM2 1 1 PWM4 PA6OutSel1 PA6OutSel0 PA6 Output Data remarks 0 0 PADOut[6] 0 1 SCLK 1 0 PWM1_N 1 1 CK_8K PA7OutSel1 PA7OutSel0 PA7 Output Data remarks 0 0 PADOut[7] 0 1 SOUT 1 0 Pr1Ck11_N 2kHz if CK_PR1=32kHz 1 1 Pr1Ck10_N 1kHz if CK_PR1=32kHz Wheras: PWM3 = PWM output of timer 3 (refer to timer section) * PWM3_N = inverse PWM output of timer 3 * Ck_Lo = Low frequency base clock (refer to clock selection) * CK_Lo_N = inverse Low frequency base clock * Pr1Ck11 = Prescaler 1, ck11 output (refer to prescaler) *
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14.4 PORT A DEBOUNCER
Each Port A input has its own debouncer with an independent clock selection. The debouncer is either transparent or clocked. The debouncer output signal is called PADeb[n] * Transparent Mode: The input is immediately available on its output. * Clocked mode: The debouncer copies is input state to its output only if during 2 consecutive debouncer clock events the debouncer input signal remains stable. The debouncer is reset on POR, in Power-Down mode, by a watchdog reset and a bus error reset. Table 14.4-1 Port A Debouncer Mode and Clock selection
PA[n]DebSel1 0 0 1 1 PA[n]DebSel0 0 1 0 1 Clock Pr1Ck7 Pr1Ck15 Pr2Ck10 no clock Mode Clocked Clocked Clocked Transparent remarks Clocked; 128 Hz if ck_pr1=32kHz Clocked; Pr1 input clock Clocked; Pr2 input clock Output = Input
14.5 PORT A INTERRUPT GENERATION
Each port A input may be used as Interrupt source with individual masking possibilities.
14.5.1 PA IRQ IN ACTIVE AND STANDBY MODE
The clocked PortA interrupt is generated in the Active and Standby modes only. * A positive or negative edge of the debouncer output signal PADeb[n] shall generate the IntPA[n]. The edge selection is done by the register bit PAIntEdg[n] (`1' means a positive edge and it's the default state). * The IntPA signal is the input to the interrupt controller.(refer to the interrupt controller for Irq masking and handling). * All interrupt settings are independent for each PA input.
14.5.2 PA IRQ IN SLEEP MODE
In Sleep mode, any edge (positive or negative) of the PA[n] input while PAInpEn[n]=1 will generate an IntPA request. * The IntPA signal is the input to the interrupt controller.(refer to the interrupt controller for Irq masking and handling). * All interrupt settings are independent for each PA input.
14.6 PORT A RESET FUNCTION
Each port A input can be used to generate a system reset (ResSys in Reset controller). * The Port A reset signal ResPA is a logical OR function of all PA input reset sources after masking. * The input signals for the port A reset function are coming from the Port A debouncer output PADeb[n] and can be masked individually with RegEnResPA[n]='0' . Default: all inputs are masked and no PA reset is generated. * The ResPA is the output of the port A reset function and the input signal to the reset controller.
14.7 PORT A WAKE-UP FUNCTION
Each port A input can be used to wake-up the circuit from Power-Down mode. * In Power-Down mode, any state change of a selected PA[n] input while its PAInpEn[n]=1 will cancel wake-up and resume to active mode. A PA[n] input is only selected for wake-up if its EnWkUp[n] bit is at high level.
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14.8 PORT A REGISTERS
0x000A Bits Name 7:0 PADIn 0x000B Bits Name 7:0 PADOut 0x000C Bits Name 7:0 PAInpE 0x000D Bits Name 7:0 PAOE 0x000E Bits Name 7:0 PAPU 0x000F Bits Name 7:0 PAPD 0x0010 Bits Name 7:0 PAOD 0x0015 Bits 7:0 Name PAIntEdg RegPADIn Type ResVal RO 0x00 RegPADOut Type ResVal RW_Res 0x00 RegPAInpE Type ResVal RW_Res 0x00 RegPAOE Type ResVal RW_Res 0x00 RegPAPU Type ResVal RW 0x00 RegPAPD Type ResVal RW 0x00 RegPAOD Type ResVal RW 0x00 RegPAIntEdg Type RW ResVal 0xFF ResSrc ResSys ResSrc ResSys Port-A Data Input Description Port-A Data Input Port-A Data Output Description Port-A Data Output Port-A Input Enable Description Port-A Input Enable Port-A Output Enable Description Port-A Output Enable Port-A Pull Up Description Port-A Pull Up Port-A Pull Down Description Port-A Pull Down Port-A Open Drain Description Port-A Open Drain Port-A Interrupt Edge Selection: 1-Rising, 0-Falling Description Port-A Interrupt Edge Selection: 1-Rising, 0-Falling Port-A Output Configuration/Selection - 0 Description Port-A3 Output Configuration/Selection Port-A2 Output Configuration/Selection Port-A1 Output Configuration/Selection Port-A0 Output Configuration/Selection Port-A Output Configuration/Selection - 1 Description Port-A7 Output Configuration/Selection Port-A6 Output Configuration/Selection Port-A5 Output Configuration/Selection Port-A4 Output Configuration/Selection Port-A Deboucer Configuration - 1 Description PA(3) Deboucer clock Selection/Enable PA(2) Deboucer clock Selection/Enable PA(1) Deboucer clock Selection/Enable PA(0) Deboucer clock Selection/Enable
ResSrc ResSys
ResSrc ResAna
ResSrc ResAna
ResSrc PorLog
ResSrc PorLog
ResSrc ResSys
0x0011 Bits Name 7:6 PA3OutSel 5:4 PA2OutSel 3:2 PA1OutSel 1:0 PA0OutSel 0x0012 Bits Name 7:6 PA7OutSel 5:4 PA6OutSel 3:2 PA5OutSel 1:0 PA4OutSel 0x0013 Bits Name 7:6 PA3DebSel 5:4 PA2DebSel 3:2 PA1DebSel 1:0 PA0DebSel
RegPAOutCfg0 Type ResVal RW `00' RW `00' RW `00' RW `00' RegPAOutCfg1 Type ResVal RW `00' RW `00' RW `00' RW `00' RegPADebCfg1 Type ResVal RW `00' RW `00' RW `00' RW `00'
ResSrc ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys
ResSrc ResAna ResAna ResAna ResAna
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0x0014 Bits Name 7:6 PA7DebSel 5:4 PA6DebSel 3:2 PA5DebSel 1:0 PA4DebSel 0x0001 Bits Name 7:0 EnResPA 0x0002 Bits Name 7:0 EnWkUpPA RegPADebCfg2 Type ResVal RW `00' RW `00' RW `00' RW `00' RegEnResPA Type ResVal RW 0x00 RegEnWkUpPA Type ResVal RW 0x00 ResSrc ResAna ResAna ResAna ResAna Port-A Deboucer Configuration - 2 Description PA(7) Deboucer clock Selection/Enable PA(6) Deboucer clock Selection/Enable PA(5) Deboucer clock Selection/Enable PA(4) Deboucer clock Selection/Enable Enable Reset by PortA bits Description Enable Reset by PortA bits Enable of Wake Up from Power-Down by PortA Description Enable of Wake Up from Power-Down by PA bits
ResSrc ResAna
ResSrc ResSys
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 15. PORT B
The port B is general purpose 8-bit input output port. Each of the 8 Port B terminals can be configured to receive either Analog or digital Input or drive out analog or digital data. The port B, PB7 and PB6 terminals, are special inputs for device programming and debugging. These 2 ports will have special configurations as soon as TM terminal is high to allow Gasp (ISP, DoC) accesses.
15.1 PORT B TERMINAL MAPPING
Several digital and analog functions are mapped on the port B terminals. Please refer also to the concerned chapters. Table 15.1-1 Port B terminal mapping
Name PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GASP-SCK GASP-SIO SOUT SCLK IRQ ADC Reset & VREF WkUp VLD OPAMP SPI SIN GASP CLOCK Timer clock Timer start PWM output FrqOut strength sig sig sig sig sig sig sig sig HD HD HD HD HD HD HD HD
15.2 PORT B IO OPERATION
All IO modes are individually selectable for each port B terminal. Refer to table below. Table 15.2-1 Port B IO selections PB[n] Output data PB[n] Terminal
PBInpE[n]
PBOE [n]
PBOD[n]
PBPU[n]
Analog signal connection (in out) Analog signal connection (in out) with weak load to VDD or VSS Input mode Input mode with pull-up Input mode with pull-down Output, CMOS high level drive Output, CMOS low level drive Output, open drain, high-Z Output, open drain with pull-up Output, open drain drive low
0 0 0 0 0 0 1 1 1 1 1
X X X X X X 1 0 1 1 0
X X X X X X 0 0 1 1 1
0 1 0 0 1 0 X X 0 1 X
0 X 1 0 X 1 X X X X X
PBPD[n]
Modes
Notes
0 0 0 1 1 1 X X X X X
High-Z RLoad to VDD RLoad to VSS High-Z Weak Hi Weak Lo 1 0 High-Z Weak Hi 0
Digital input is blocked, Analog functions can be connected CPU reads `0' Digital input, no-pull, needs external driver Digital input with pullup Digital input with pulldown Pull resistors disabled Pull resistors disabled Pull-down disabled, Usually ext Resistor pull-up Pull-up active Pull-up disabled
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Figure 13; Port B IO configuration
* * * *
For maximum flexibility all Port B configuration bits are are fully user configurable. The pull resistors are only active if the pad driver is not driving the pad terminal, and pullup or pulldown resistors are enabled. Pullup has priority over pulldown. The CPU read of the port B terminal logic value (PB[n]) in register RegPBDIn is depending of the PBInpEn blocking bit. As such one reads `0' if PBInpEn='0' (Input blocked) and the terminal logic value if PBInpEn='1'. At power-up, the PB[n] terminals are tristate with pullup and pulldown resistors disconnected and the input is disabled. As such all PB terminal can float without the penalty of additional power consumption.
Note: Make sure to setup the terminal correctly before using it..
15.2.1 GASP COMMUNICATION ON PB7, PB6
As soon as TM terminal becomes high the terminal PB7 and PB6 configurations are forced by the Gasp module without altering the port B register settings. Gasp mode has priority over normal IO mode on these 2 terminals.
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15.3 OUTPUT SIGNALS ON PORT B
Different internal clock frequencies and PWM signals can be outout on all port B terminals. (PB[n] Output data) * The selection is done with the registers PB[n]OutSel1,0 . All clock outputs (Pr1ckx, Pr2ckx) have a 50% duty cycle. The Clock outputs CK_x have a duty cycle corresponding to the duty cycle of their clock source. * By default the register data PBDOut[n] value is seleted as data output. * Data is only output if the corresponding PBOutEn[n] bit is high. Table 15.3-1 Port B Output signal selection remarks PB0OutSel1 PB0OutSel0 PB0 Output Data 0 0 PBDOUT[0] 0 1 PWM3 1 0 PWM2 1 1 PWM4 remarks PB1OutSel1 PB1OutSel0 PB1 Output Data 0 0 PBDOUT[1] 0 1 PWM3_N 1 0 PWM2_N 1 1 PWM4_N remarks PB2OutSel1 PB2OutSel0 PB2 Output Data 0 0 PBDOUT[2] 0 1 SCLK 1 0 PWM1 1 1 PWM3 remarks PB3OutSel1 PB3OutSel0 PB3 Output Data 0 0 PBDOUT[3] 0 1 CK_Hi 1 0 PWM1_N 1 1 PWM3_N remarks PB4OutSel1 PB4OutSel0 PB4 Output Data 0 0 PBDOUT[4] 0 1 SOUT 1 0 PWM1 1 1 PWM3 remarks PB5OutSel1 PB5OutSel0 PB5 Output Data 0 0 PBDOUT[5] 0 1 PWM3 1 0 PWM2 1 1 PWM4 remarks PB6OutSel1 PB6OutSel0 PB6 Output Data 0 0 PBDOUT[6] 0 1 PWM1_N 1 0 PWM3_N 1 1 Pr1Ck11 2kHz if CK_PR1=32kHz remarks PB7-OutSel1 PB7-OutSel0 PB7 Output Data 0 0 PBDOUT[7] 0 1 PWM1 1 0 PWM3 1 1 Pr1Ck10 1kHz if CK_PR1=32kHz Wheras: PWM3 = PWM output of timer 3 (refer to timer section) * PWM3_N = inverse PWM output of timer 3 * Ck_Hi = High frequency base clock (refer to clock selection) * Pr1Ck10 = Prescaler 1, ck10 output (refer to prescaler) *
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15.4 PORT B REGISTERS
0x0016 Bits Name 7:0 PBDIn 0x0017 Bits Name 7:0 PBDOut 0x0018 Bits Name 7:0 PBInpE 0x0019 Bits Name 7:0 PBOE 0x001A Bits Name 7:0 PBPU 0x001B Bits Name 7:0 PBPD 0x001C Bits Name 7:0 PBOD 0x001D Bits Name 7:6 PB3OutSel 5:4 PB2OutSel 3:2 PB1OutSel 1:0 PB0OutSel 0x001E Bits Name 7:6 PB7OutSel 5:4 PB6OutSel 3:2 PB5OutSel 1:0 PB4OutSel RegPBDin Type ResVal RO 0x00 RegPBDOut Type ResVal RW_Res 0x00 RegPBInpE Type ResVal RW_Res 0x00 RegPBOE Type ResVal RW_Res 0x00 RegPBPU Type ResVal RW_Res 0x00 RegPBPD Type ResVal RW_Res 0x00 RegPBOD Type ResVal RW_Res 0x00 RegPBOutCfg0 Type ResVal RW '00' RW '00' RW '00' RW '00' RegPBOutCfg1 Type ResVal RW '00' RW '00' RW '00' RW '00' ResSrc ResSys Port-B Data Input Description Port-B Data Input Port-B Data Output Description Port-B Data Output Port-B Input Enable Description Port-B Input Enable Port-B Output Enable Description Port-B Output Enable Port-B Pull Up Description Port-B Pull Up Port-B Pull Down Description Port-B Pull Down Port-B Open Drain Description Port-B Open Drain Port-B Output Configuration/Selection - 0 Description Port-B3 Output Configuration/Selection Port-B2 Output Configuration/Selection Port-B1 Output Configuration/Selection Port-B0 Output Configuration/Selection Port-B Output Configuration/Selection - 1 Description Port-B7 Output Configuration/Selection Port-B6 Output Configuration/Selection Port-B5 Output Configuration/Selection Port-B4 Output Configuration/Selection
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc PorLog
ResSrc PorLog
ResSrc ResSys
ResSrc ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys
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The port C is general purpose 8-bit input output port. Each of the 8 Port C terminals can be configured to receive either Analog or digital Input or drive out analog or digital data.
16.1 PORT C TERMINAL MAPPING
Several digital and analog functions are mapped on the port C terminals. Please refer also to the concerned chapters. Table 16.1-1 Port C terminal mapping
Name PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 IRQ ADC Reset & VREF VLD WkUp OPAMP SPI CLOCK Timer clock Timer start PWM output FrqOut strength sig VLD OPA_Out OPA_INM SOUT OPA_INP XOUT ExtCk VLD VLD SCLK t1ck1_in start7_in t3ck1_in t4ck1_in start6_in t2ck1_in start3_in sig sig sig sig sig sig sig HD HD HD
PCIRQ0 ADC1 PCIRQ1 ADC3 PAIRQ2 ADC5 PCIRQ3 ADC7 PCIRQ4 PCIRQ5 PCIRQ6 PCIRQ7
16.2 PORT C IO OPERATION
All IO modes are individually selectable for each port C terminal. Refer to table below. Table 16.2-1 Port C IO selections PC[n] Output data PC[n] Terminal
PCInpE[n]
PCOE [n]
PCOD[n]
PCPU[n]
Analog signal connection (in out) Analog signal connection (in out) with weak load to VDD or VSS Input mode Input mode with pull-up Input mode with pull-down Output, CMOS high level drive Output, CMOS low level drive Output, open drain, high-Z Output, open drain with pull-up Output, open drain drive low
0 0 0 0 0 0 1 1 1 1 1
X X X X X X 1 0 1 1 0
X X X X X X 0 0 1 1 1
0 1 0 0 1 0 X X 0 1 X
0 X 1 0 X 1 X X X X X
PCPD[n]
Modes
Notes
0 0 0 1 1 1 X X X X X
High-Z RLoad to VDD RLoad to VSS High-Z Weak Hi Weak Lo 1 0 High-Z Weak Hi 0
Digital input is blocked, Analog functions can be connected CPU reads `0' Digital input, no-pull, needs external driver Digital input with pullup Digital input with pulldown Pull resistors disabled Pull resistors disabled Pull-down disabled, Usually ext Resistor pull-up Pull-up active Pull-up disabled
Note: on all bit of port C debouncers are enable by default after reset,
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Figure 14; Port C IO configuration
PC IO configuration architecture
PCPU[n]
ANALOG IO
PCOD[n]
70 KOhm
PCDOut[n] clocks clocks clocks
Read RegPADin
PA[n] output data
PC[n]
PADIn[n] Data-bus
PC[n]OutSel1,0 PCInpEn[n] Debouncer
70 KOhm
PCDeb[n] PC input data to: - timer - SPI - PC-IRQ
PC[n]DebSel1,0 ck
-clocked mode -transparent mode
PCPD[n]
* * * * *
For maximum flexibility all Port C configuration bits are are fully user configurable. The pull resistors are only active if the pad driver is not driving the pad terminal, and pullup or pulldown resistors are enabled. Pullup has priority over pulldown. The CPU read of the port C terminal logic value (PC[n]) in register RegPCDIn is depending of the PCInpEn blocking bit. As such one reads `0' if PCInpEn='0' (Input blocked) and the terminal logic value if PCInpEn='1'. At power-up, the PC[n] terminals are tristate with pullup and pulldown resistors disconnected and the input is disabled. As such all PC terminal can float without the penalty of additional power consumption. All PC input signal sources for Timer, SPI, PC-IRQ are coming from the debouncer output PCDeb[n].
Note: Make sure to setup the terminal correctly before using it as either digital IO or as an analog connection.
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16.3 OUTPUT SIGNALS ON PORT C
Different internal clock frequencies and PWM signals can be outout on all port C terminals. (PA[n] Output data) * The selection is done with the registers PC[n]OutSel1,0 . All clock outputs (Pr1ckx, Pr2ckx) have a 50% duty cycle. The Clock outputs CK_x have a duty cycle corresponding to the duty cycle of their clock source. * By default the register data PCDOut[n] value is seleted as data output. * Data is only output if the corresponding PCOutEn[n] bit is high. Table 16.3-1 Port C Output signal selection
remarks PC0OutSel1 PC0OutSel0 PC0 Output Data 0 0 PCDOUT[0] 0 1 Pr2Ck6 125kHz if CK_PR2=2MHz 1 0 Pr2Ck4 31kHz if CK_PR2=2MHz 1 1 Pr2Ck0 2kHz if CK_PR2=2MHz remarks PC1OutSel1 PC1OutSel0 PC1 Output Data 0 0 PCDOUT[1] 0 1 PWM4_N 1 0 PWM1_N 1 1 PWM3_N remarks PC2OutSel1 PC2OutSel0 PC2 Output Data 0 0 PCDOUT[2] 0 1 SOUT 1 0 PWM1_N 1 1 Ck_Lo remarks PC3OutSel1 PC3OutSel0 PC3 Output Data 0 0 PCDOUT[3] 0 1 CK_LO_N 1 0 Pr1Ck11_N 2kHz if CK_PR1=32kHz 1 1 Pr1Ck10_N 1kHz if CK_PR1=32kHz remarks PC4OutSel1 PC4OutSel0 PC4 Output Data 0 0 PCDOUT[4] 0 1 Ck_Hi 1 0 Pr2Ck6 125kHz if CK_PR2=2MHz 1 1 Pr2Ck4 31kHz if CK_PR2=2MHz remarks PC5OutSel1 PC5OutSel0 PC5 Output Data 0 0 PCDOUT[5] 0 1 CK_8K 1 0 Pr2Ck6 125kHz if CK_PR2=2MHz 1 1 Pr2Ck4 31kHz if CK_PR2=2MHz remarks PC6OutSel1 PC6OutSel0 PC6 Output Data 0 0 PCDOUT[6] 0 1 SCLK 1 0 PWM1_N 1 1 ck_lo remarks PC7OutSel1 PC7OutSel0 PC7 Output Data 0 0 PCDOUT[7] 0 1 PWM1 1 0 PWM3_N 1 1 Pr1Ck12 4kHz if CK_PR1=32kHz Wheras: PWM1 = PWM output of timer 1 (refer to timer section) * PWM1_N = inverse PWM output of timer 1 * Ck_Hi = High frequency base clock (refer to clock selection) * Pr1Ck12 = Prescaler 1, ck12 output (refer to prescaler) *
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16.4 PORT C DEBOUNCER
Each Port C input has its own debouncer with an independent clock selection. The debouncer is either transparent or clocked. The debouncer output signal is called PCDeb[n]. * Transparent Mode: The input is immediately available on its output. * Clocked mode: The debouncer copies is input state to its output only if during 2 consecutive debouncer clock events the debouncer input signal remains stable. The debouncer is reset on POR, in Power-Down mode, by a watchdog reset and a bus error reset.
Table 16.4-1 Port C Debouncer Mode and Clock selection PC[n]DebSel1 PC[n]DebSel0 Clock 0 0 Pr1Ck7 0 1 Pr1Ck15 1 0 Pr2Ck10 1 1 no clock
Mode Clocked Clocked Clocked Transparent
remarks Clocked; 128 Hz if ck_pr1=32kHz Clocked; Pr1 input clock Clocked; Pr2 input clock Output = Input
16.5 PORT C INTERRUPT GENERATION
Each port C input may be used as Interrupt source with individual masking possibilities.
16.5.1 PC IRQ IN ACTIVE AND STANDBY MODE
The clocked port C interrupt is generated in the Active and Standby modes only. * A positive or negative edge of the debouncer output signal PCDeb[n] shall generate the IntPC[n] interrupt request. The edge selection is done by the register bit PCIntEdg[n] (`1' means a positive edge and it's the default state). * The IntPC signal is the input to the interrupt controller. (Refer to the interrupt controller for Irq masking and handling). * All interrupt settings are independent for each PC input.
16.5.2 PC IRQ IN SLEEP MODE
There is no port C interrupt possibility in Sleep mode. Port C interrupt input will automatically switch to the corresponding port A in Sleep mode. Refer also to the interrupt controller section 10
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16.6 PORT C REGISTERS
0x001F Bits Name 7:0 PCDIn 0x0020 Bits Name 7:0 PCDOut 0x0021 Bits Name 7:0 PCInpE 0x0022 Bits Name 7:0 PCOE 0x0023 Bits Name 7:0 PCPU 0x0024 Bits Name 7:0 PCPD 0x0025 Bits Name 7:0 PCOD 0x002A Bits 7:0 Name PCIntEdg RegPCDin Type ResVal RO 0x00 RegPCDOut Type ResVal RW_Res 0x00 RegPCInpE Type ResVal RW_Res 0x00 RegPCOE Type ResVal RW_Res 0x00 RegPCPU Type ResVal RW_Res 0x00 RegPCPD Type ResVal RW_Res 0x00 RegPCOD Type ResVal RW_Res 0x00 RegPCIntEdg Type RW ResVal 0xFF ResSrc ResSys ResSrc ResSys Port-C Data Input Description Port-C Data Input Port-C Data Output Description Port-C Data Output Port-C Input Enable Description Port-C Input Enable Port-C Output Enable Description Port-C Output Enable Port-C Pull Up Description Port-C Pull Up Port-C Pull Down Description Port-C Pull Down Port-C Open Drain Description Port-C Open Drain Port-C Interrupt Edge Selection: 1-Rising, 0-Falling Description Port-C Interrupt Edge Selection: 1-Rising, 0-Falling Port-C Output Configuration/Selection - 0 Description Port-C3 Output Configuration/Selection Port-C2 Output Configuration/Selection Port-C1 Output Configuration/Selection Port-C0 Output Configuration/Selection Port-C Output Configuration/Selection - 1 Description Port-C7 Output Configuration/Selection Port-C6 Output Configuration/Selection Port-C5 Output Configuration/Selection Port-C4 Output Configuration/Selection Port-C Deboucer Configuration - 1 Description PC(3) Deboucer clock Selection/Enable PC(2) Deboucer clock Selection/Enable PC(1) Deboucer clock Selection/Enable PC(0) Deboucer clock Selection/Enable
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc PorLog
ResSrc PorLog
ResSrc ResSys
0x0026 Bits Name 7:6 PC3OutSel 5:4 PC2OutSel 3:2 PC1OutSel 1:0 PC0OutSel 0x0027 Bits Name 7:6 PC7OutSel 5:4 PC6OutSel 3:2 PC5OutSel 1:0 PC4OutSel 0x0028 Bits Name 7:6 PC3DebSel 5:4 PC2DebSel 3:2 PC1DebSel 1:0 PC0DebSel
RegPCOutCfg0 Type ResVal RW '00' RW '00' RW '00' RW '00' RegPCOutCfg1 Type ResVal RW '00' RW '00' RW '00' RW '00' RegPCDebCfg1 Type ResVal RW '00' RW '00' RW '00' RW '00'
ResSrc ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys
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0x0029 Bits Name 7:6 PC7DebSel 5:4 PC6DebSel 3:2 PC5DebSel 1:0 PC4DebSel RegPCDebCfg2 Type ResVal RW '00' RW '00' RW '00' RW '00' ResSrc ResSys ResSys ResSys ResSys Port-C Deboucer Configuration - 2 Description PC(7) Deboucer clock Selection/Enable PC(6) Deboucer clock Selection/Enable PC(5) Deboucer clock Selection/Enable PC(4) Deboucer clock Selection/Enable
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 17. TIMERS
The circuit contains 4 independent 8-bit timers configurable as 2 16-bit timers. * Each of it can be individually configured with: * 6 internal clock sources and 2 external clock sources from PA, PC terminals * Individual Start/Stop selection by SW or from various IO terminals * Timer interrupt selection * Auto-reload(free-running) and Auto-Stop mode * Input Capture on hardware events (terminal input) or SW driven * Output Compare for signal generation * PWM and Frequency output * RTZ, RTO output clock capabilities * Timer outputs mapping on various IO terminals * Always also provides complementary level output to increase overall voltage swing. The timers are implemented as up-counters, counting from 0x00 to RegTimXFull or as a free running counter cycling from 0x00 to RegTimXFull. If the full value changes while the timer is running, the previous full value will be used for the full event detection. The new full value will be used for the next counting cycle. The timer status value (actual count value) is readable in registers RegTimXStatus.
17.1 TIMER CHAINING
Possible configurations are: * Timer1, Timer2, Timer3, Timer4 used independently * Timer1 and Timer2 chained together (Timer12); Timer3 and Timer 4 used independently * Timer1 and Timer2 used independently; Timer3 and Timer4 chained (=Timer34) * Timer1 and Timer2 chained together (Timer12); Timer3 and Timer4 chained (=Timer34) Timer1 and Timer2 are chained and able to work as 16-bits timer when Tim12Chain in RegTimersCfg is high. In this case, the configuration is set by the Timer1 and Timer2 (slave) is the MSB. Timer3 and Timer4 are chained and able to work as 16-bits timer when Tim34Chain in RegTimersCfg is high. In this case, the configuration is set by the Timer3 and Timer4 (slave) is the MSB. Figure 15, Timer chaining
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17.2 TIMER CLOCK SOURCES
The timer clock inputs connect directly to the prescaler1 and prescaler2 outputs. The prescalers themselves connect to Ck_Hi or Ck_Lo which are derived from the internal RC oscillators or the external clock sources from XTAL, Resonator or PC4 input. Please refer to the chapter Clock selection and Clock switching for more details about the basic clock setup. Additionaly to the prescaler clock sources the timers may also run on 2 external clocks sources, one from PA the other from PC. The clock source selection is done in registers RegTimXCfg bits TimXSelClk as follows (X stands for 1,2,3,4) Table 17.2-1 Timer clock configuration Tim1SelClk Timer1, Tim2SelClk Timer2 Tim3SelClk Timer3, Tim4SelClk Timer4 [2:0] Timer12 [2:0] [2:0] Timer34 [2:0] 000 PA0 000 PA1 000 PA2 000 PA3 001 PC6 001 PC1 001 PC7 001 PC3 010 Pr2Ck10 010 Pr2Ck10 010 Pr2Ck10 010 Pr2Ck10 011 Pr2Ck8 011 Pr1Ck15 011 Pr2Ck8 011 Pr1Ck15 100 Pr2Ck6 100 Pr1Ck14 100 Pr2Ck4 100 Pr1Ck13 101 Pr1Ck15 101 Pr1Ck12 101 Pr1Ck15 101 Pr1Ck11 110 Pr1Ck13 110 Pr1Ck10 110 Pr1Ck13 110 Pr1Ck9 111 Pr1Ck11 111 Pr1Ck8 111 Pr1Ck9 111 Pr1Ck7 Maximal external timer input clock frequency must be lower than to Ck_Hi/2 or Ck_Lo/2 if Ck_Hi is not used. Table 17.2-2 Timer clock configuration overview (decimal values of TimXSelClk) TimXSelClk Tim1-Ck, Tim3-Ck Tim2-Ck Tim4-Ck [2:0] Tim12-Ck Tim34-Ck Timer ck selection to Prescaler 1 freq Pr1Ck15 5 3 5 3 Pr1Ck14 4 Pr1Ck13 6 6 4 Pr1Ck12 5 Pr1Ck11 7 5 Pr1Ck10 6 Pr1Ck9 7 6 Pr1Ck8 7 Pr1Ck7 7 Timer ck selection to Prescaler 2 freq Pr2Ck10 2 2 2 2 Pr2Ck9 Pr2Ck8 3 3 Pr2Ck7 Pr2Ck6 4 Pr2Ck5 Pr2Ck4 4 Timer ck selection to PA input clocks PA[0] 0 PA[1] 0 PA[2] 0 PA[3] 0 PC[1] 1 PC[3] 1 PC[6] 1 PC[7] 1
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17.3 TIMER START
The timers can be started and stopped by SW or hardware events. To be able to start the RegTimXFull value must not be equal to 0x00. All timer settings must be performed before starting the timer. The timer start and stop selection are done in registers RegTimXCfg bits TimXSelStart as follows: Table 17.3-1 Timer start selection TimXSelStart Timer1, Timer3, Timer2 Timer4 [2:0] Timer12 Timer34 000 SW start SW start SW start SW start Hardware start - stop selections 001 010 011 100 101 110 111 PA0 PA1 PC1 PA2 PA3 PC3 PC6 PA0 PA1 PC1 PA2 PA3 PC3 PC6 PA0 PA1 PC1 PA2 PA3 PC3 PC6 PA0 PA1 PC1 PA2 PA3 PC3 PC6
Notes: External start/stop signal must be glitch free and debouncer must be used to ensure that no glitch is propagated to the timer * When the debouncer is used, then start/stop pulse width should be longer than two clock periods of the debouncer, otherwise incoming pulse is suppressed. * Minimal pulse width of external start/stop signal has to be longer than one timer clock period when debouncer is bypassed.
Figure 16, Timer SW and Hardware (Pulse, Period) Start-Stop
17.3.1 SOFTWARE START - STOP
In case of software start selection (TimXSelStart='000') the timers will start counting from 0x00 as soon as TimXSWStart in RegTimersStart goes to high level. When TimXSWStart goes to low level, the timerX will stop counting and RegTimXStatus keeps its status value.
17.3.2 HARDWARE START - STOP (PERIOD COUNTING)
In case of hardware start selection (TimXSelStart <> 000) and TimXPulse in RegTimersStart is high, the timer will start counting from 0x00 as soon as the selected external start input ExtTimXStart goes to high level. When another pulse occurs on ExtTimXStart, timerX shall stop to count and RegTimXStatus keeps its status.
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Notes: External start/stop period must be glitch free and debouncer must be used to ensure that no glitch is propagated to the timer * When the debouncer is used then the pulses width (pulse at `1' and pulse at `0' of PXDIn) should be longer than two clock periods of the debouncer, (otherwise incoming pulse is suppressed). * When the debouncer is bypassed, the period of the measured signal (PXDeb) has to be longer than one timer clock period: the timer is able to count the period of the incoming signal if its period is longer than one timer clock period (otherwise the timer is reloaded only). * These two conditions need to be fulfilled when the debouncer is enabled and external period needs to be measured (Refer to Figure 12; Port A IO configuration and Figure 14; Port C IO configuration)
17.3.3 HARDWARE START - STOP (PULS COUNTING)
In case of hardware start selection (TimXSelStart <> `000') and TimXPulse in RegTimersStart is low, the timer will start counting from 0x00 on the first positive pulse on the selected external start input ExtTimXStart. When ExtTimXStart goes back to low level, timerX will stop to count and RegTimXStatus keeps its status. Notes: External start/stop pulse must be glitch free and debouncer must be used to ensure that no glitch is propagated to the timer * When the debouncer is used then the pulse width (PXDIn) should be longer than two clock periods of debouncer (otherwise incoming pulse is suppressed) * When the debouncer is bypassed, the start/stop signal pulse width (pulse measurement of PXDeb) has to be longer than one timer clock period: the timer is able to count the pulse width of the incoming signal if its width is longer than one timer clock period (otherwise the timer is reloaded only). * These two conditions need to be fulfilled when the debouncer is enabled and external pulse width needs to be measured (Refer to Figure 12; Port A IO configuration and Figure 14; Port C IO configuration)
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17.4 AUTO-RELOAD MODE
In autoreload mode the timerX always restart counting from 0x00 once its status reaches TimXFull value. It will act as a free running counter. Going into Auto-reload mode: * By setting the corresponding TimXAR bit in register RegTimersCfg at high level. Canceling Auto-Reload mode * By a sytem reset, stopp immediately, TimXStatus cleared. * By a removed start condition, stopp immediately, TimXStatus maintained. * By TimXAR written to `0', stopp after reaching TimXFull value. Figure 17, Sample waveforms in Auto-Reload mode
17.5 AUTO-STOP MODE
In auto-stop mode the timerX counts from 0x00 until it reaches TimXFull value. Going into Auto-Stop mode: * By setting the corresponding TimXAR bit in register RegTimersCfg at low level. Stopping the timer * By a sytem reset, stopp immediately, TimXStatus cleared. * Removed Start condition, stopp immediately, TimXStatus maintained. * The timerX automatically stopps when reaching TimXFull value. Figure 18, Sample waveforms in Auto-Stop mode
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17.6 TIMER INPUT CAPTURE
The input capture system allows taking a timer snapshot based on an internal SW event or an external hardware event by writing the timer status value into the capture register at the occurrence of the capture event. An Interrupt IntTimX is generated on all active hardware capture events. Capture events are ignored if the timer is not running. Valid capture events are: * Software SW capture (on Timer1, Timer12, Timer3 and Timer34 only) * Hardware capture on all timers, Falling edge * Hardware capture on all timers, Rising edge * Hardware Capture on all timers, Both edges In SW capture, the event is generated by writing `1' to the bit Tim1SWCpt in register RegTimersCfg.Tim1SWCpt Timer3 by wiriting `1' to the bit Tim3SWCpt in register RegTimersCfg.Tim3SWCpt. In hardware capture the active capture inputs are selected in register RegTimXCptCmpCfg bits TimXCptCptEvtSrc as follows: Tim1CptEvtSrc[1:0] External event Tim2CptEvtSrc[1:0] External event 00 PA2 00 PA2 01 COMP 01 PA1 10 VLD 10 PA3 11 PA1 11 VLD Tim3CptEvtSrc[1:0] 00 01 10 11 External event PA2 COMP PC4 PA3 Tim4CptEvtSrc[1:0] 00 01 10 11 External event PC7 PC0 PA0 VLD
In hardware caputure the active edge(s) of the selected event source is defined by register RegTimXCptCmpCfg bits TimXCptEdg as follows: TimXCptEdg Selected edge for event signal 00 no action 01 falling edge 10 rising egde 11 both edges Figure 19, Input Capture Architecture
Timer Capture Configuration
TimXCptEvtSrc[1:0]
X = 1,2,3,4
TimXCptEdg[1:0]
X = 1,2,3,4
CptEvtSrc0 CptEvtSrc1 CptEvtSrc2 CptEvtSrc3
0 1 MUX 2 4:1 3
Edge detector Rising edge
0 1 MUX 2 4:1 3
load
CptXInt
Edge detector Falling edge
RegTimXStatus
TimX-Ck ck
Edge detector both edges
RegTimXCptVal
Software Capture via TimXSWCpt
X = 1,3
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Notes: External input capture event must be glitch free and debouncer must be used to ensure that no glitch is propagated to the timer * When the debouncer is used then the pulse width of external capture signal (PXDIn) should be longer than two clock periods of the debouncer (otherwise incoming pulse is suppressed) * When the debouncer is bypassed then the pulse width of external capture signal (PXDeb) has to be longer than one timer clock period (otherwise an invalid value could be loaded to the capture register) * These two conditions need to be fulfilled when the debouncer is enabled and external input capture event need to be captured (Refer to Figure 12; Port A IO configuration and Figure 14; Port C IO configuration)
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17.7 OUTPUT COMPARE
The output compare function allows generating a multitude of different output signal waveforms. PWM, variable or fix frequencies, RTZ (Return To Zero clocks), RTO (Return To One clocks) to name just a few. It may also be used to encode serial protocols i.e Manchester encoding. The compare function is enabled by setting bit TimXEnPWM in register RegTimXCfg to `1'. The compare function uses the PWMX signal of the timer. At system reset PWMX is forced low. PWMX will maintain its last status when the corresponding TimXEnPWM ='0'. Whenever the timer reaches RegTimXFull or RegTimXCmpVal an action may be performed on PWMX. The action is defined by TimXCmpFullAct when it reaches RegTimXFull and by TimXCmpValAct when it reaches RegTimXCmpVal as defined in tables below: (TimXCmpFullAct action has a priority). Successive comparisons may be made. Output compare usually is used in Auto-Reload mode (free running counter). Figure 20, Output Compare Description
PWM, RTZ, RTO
1 or several compares within the fix load period
Successive compare value (CmpVal)
Full value (CmpFull)
0
Auto-Reload mode CmpFull: counter value = full value
CmpVal: counter value = compare value Full Period = full value + 1 Ratio = compare value / (full value + 1) Full value + 1 Compare value
1st compare value (CmpVal)
Successive compare
Possible signal transitions CmpXVal CmpXFull
TimXCmpValAct 00 01 10 11
Action when timerX reaches RegTimXCmpVal No action on PWMX Force 0 on PWMX Force 1 on PWMX Toggle PWMX
TimXCmpFullAct 00 01 10 11
Action when timerX reaches RegTimXFull No action on PWMX Force 0 on PWMX Force 1 on PWMX Toggle PWMX
Figure 21, Output Compare Architecture TimXCmpFullAct[1:0] TimXCmpValAct[1:0]
TimXFull CmpXFull TimXStatus CmpXVal TimXCmpVal TimXEnPWM X = 1, 2, 3, 4 En
State Machine Force `1' Force `0' Toggle No Action
PWMX_N PWMX
OutSel OE
PA PB PC
InpEn
ResSys
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17.8 OUTPUT COMPARE - PWMX SIGNAL PORT MAPPING
Mapping of the timers PWM signal to the port A, B and C terminals.
The port mapping is made in such a way that usually one has the PWMX and its complementary output PWMX_N available. Using the differential output voltages between PWMX and PWMX_N the output drive energy increases by a factor 4. Figure 22, PWMX complementary outputs
PortA PWM1 PWM_1N PWM2 PWM_2N PWM3 PWM_3N PWM4 PWM_4N PortC PWM1 PWM_1N PWM2 PWM_2N PWM3 PWM_3N PWM4 PWM_4N PortB PWM1 PWM_1N PWM2 PWM_2N PWM3 PWM_3N PWM4 PWM_4N
PA0
PA1 X
PA2 X
PA3
PA4
PA5
PA6 X
PA7
X X X X X PC0 PC1 X PC2 X PC3 PC4 PC5 PC6 X PC7 X X X
The corresponding port setup must be made to allow the PWMX and PWMX_N signal to output on the mapped port terminal.
X X PB0 PB1 PB2 X PB3 X X X X X X X X X X X X X X PB4 X PB5 PB6 X
X
PB7 X
X
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17.9 TIMER INTERRUPTS
Timer interrupts may be generated on hardware capture events, when the timer reaches the compare value and when the timer reaches the full value. The timer interrupt generation is totally independent of the different timer mode settings. Interrupt generation when: * The CmpFull interrupt is only generated when TimXIntSel in register RegTimXCfg is `0', and the counter reaches the TimXFull value * The CmpVal interrupt is only generated when TimXIntSel in register RegTimXCfg is `1', and the counter reaches the TimXCmpVal value * The capture interrupt is always generated if a valid hardware input capture event is applied to the selected input source. Figure 23, Timer Interrupt structure
17.10
TIMER REGISTERS
RegTimersCfg Type ResVal RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 OS 0 OS 0 RegTimersStart Type ResVal STS 0 RW 0 STS RW STS RW STS RW 0 0 0 0 0 0 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys Timers Configuration Description Chain Timer1 & Timer2 into one 16bit Timer Chain Timer3 & Timer4 into one 16bit Timer Autoreload mode of Timer1 Autoreload mode of Timer2 Autoreload mode of Timer3 Autoreload mode of Timer4 Timer1/12 SW event for Capture Timer3/34 SW event for Capture Timers Start Event Configuration Description Start/Run Timer1 by SW 1-Start-Stop Timer1 by Event, 0-Enable/Run by active level Start/Run Timer2 by SW 1-Start-Stop Timer2 by Event, 0-Enable/Run by active level Start/Run Timer3 by SW 1-Start-Stop Timer3 by Event, 0-Enable/Run by active level Start/Run Timer4 by SW 1-Start-Stop Timer4 by Event, 0-Enable/Run by active level
0x003B Bits Name 7 Tim12Chain 6 Tim34Chain 5 Tim1AR 4 Tim2AR 3 Tim3AR 2 Tim4AR 1 Tim1SWCpt 0 Tim3SWCpt 0x003C Bits Name 7 Tim1SWStart 6 Tim1Pulse 5 4 3 2 1 0 Tim2SWStart Tim2Pulse Tim3SWStart Tim3Pulse Tim4SWStart Tim4Pulse
ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ResSys ResSys
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0x003D Bits Name 7 Tim1EnPWM 6 Tim1IntSel 5:3 Tim1SelStart 2:0 Tim1SelClk 0x003E Bits 7:6 5:4 3:2 1:0 Name Tim1CptEdg Tim1CptEvtSrc Tim1CmpFullAct Tim1CmpValAct RegTim1Cfg Type ResVal RW 0 RW 0 RW '000' RW '000' RegTim1CptCmpCfg Type RW RW RW RW ResVal '00' '00' '00' '00' ResSrc ResSys ResSys ResSys ResSys ResSrc ResSys ResSys ResSys ResSys Timer1 Configuration Description Enable PWM function of Timer1 0-Int. on Full value, 1-Int. on Compare value Start source selection Clock source selection Timer1 Compare & Capture functions configuration Description Capture event Edge Selection Capture Event External Source Selection. Action selection on PWM1 when status reaches Load value Action selection on PWM1 when status reaches Compare value Timer1 Status Description Timer1 Status Timer1 Full / End Of Count value Description Timer1 Full / End Of Count value Timer1 Compare Value Description Timer1 Compare Value Timer1 Captured Value Description Timer1 Captured Value Timer2 Configuration Description Enable PWM function of Timer2 0-Int. on Full value, 1-Int. on Compare value Start source selection Clock source selection Timer2 Compare & Capture functions configuration Description Capture event Edge Selection Capture Event External Source Selection. Action selection on PWM2 when status reaches Load value Action selection on PWM2 when status reaches Compare value Timer2 Status Description Timer2 Status Timer2 Full / End Of Count value Description Timer2 Full / End Of Count value
0x003F Bits Name 7:0 Tim1Status 0x0040 Bits Name 7:0 Tim1Full 0x0041 Bits Name 7:0 Tim1CmpVal 0x0042 Bits Name 7:0 Tim1CptVal 0x0043 Bits Name 7 Tim2EnPWM 6 Tim2IntSel 5:3 Tim2SelStart 2:0 Tim2SelClk 0x0044 Bits 7:6 5:4 3:2 1:0 Name Tim2CptEdg Tim2CptEvtSrc Tim2CmpFullAct Tim2CmpValAct
RegTim1Status Type ResVal RO 0x00 RegTim1Full Type ResVal RW 0xFF RegTim1CmpVal Type ResVal RW 0x00 RegTim1CptVal Type ResVal RO 0x00 RegTim2Cfg Type ResVal RW 0 RW 0 RW '000' RW '000' RegTim2CptCmpCfg Type RW RW RW RW ResVal '00' '00' '00' '00'
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys
0x0045 Bits Name 7:0 Tim2Status 0x0046 Bits Name 7:0 Tim2Full
RegTim2Status Type ResVal RO 0x00 RegTim2Full Type ResVal RW 0xFF
ResSrc ResSys
ResSrc ResSys
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0x0047 Bits Name 7:0 Tim2CmpVal 0x0048 Bits Name 7:0 Tim2CptVal 0x0049 Bits Name 7 Tim3EnPWM 6 Tim3IntSel 5:3 Tim3SelStart 2:0 Tim3SelClk 0x004A Bits 7:6 5:4 3:2 1:0 Name Tim3CptEdg Tim3CptEvtSrc Tim3CmpFullAct Tim3CmpValAct RegTim2CmpVal Type ResVal RW 0x00 RegTim2CptVal Type ResVal RO 0x00 RegTim3Cfg Type ResVal RW 0 RW 0 RW '000' RW '000' RegTim3CptCmpCfg Type RW RW RW RW ResVal '00' '00' '00' '00' ResSrc ResSys ResSys ResSys ResSys ResSrc ResSys Timer2 Compare Value Description Timer2 Compare Value Timer2 Captured Value Description Timer2 Captured Value Timer3 Configuration Description Enable PWM function of Timer3 0-Int. on Full value, 1-Int. on Compare value Start source selection Clock source selection Timer3 Compare & Capture functions configuration Description Capture event Edge Selection Capture Event External Source Selection. Action selection on PWM3 when status reaches Load value Action selection on PWM3 when status reaches Compare value Timer3 Status Description Timer3 Status Timer3 Full / End Of Count value Description Timer3 Full / End Of Count value Timer3 Compare Value Description Timer3 Compare Value Timer3 Captured Value Description Timer3 Captured Value Timer4 Configuration Description Enable PWM function of Timer4 0-Int. on Full value, 1-Int. on Compare value Start source selection Clock source selection Timer4 Compare & Capture functions configuration Description Capture event Edge Selection Capture Event External Source Selection. Action selection on PWM4 when status reaches Load value Action selection on PWM4 when status reaches Compare value
ResSrc ResSys
ResSrc ResSys ResSys ResSys ResSys
0x004B Bits Name 7:0 Tim3Status 0x004C Bits Name 7:0 Tim3Full 0x004D Bits Name 7:0 Tim3CmpVal 0x004E Bits Name 7:0 Tim3CptVal 0x004F Bits Name 7 Tim4EnPWM 6 Tim4IntSel 5:3 Tim4SelStart 2:0 Tim4SelClk 0x0050 Bits 7:6 5:4 3:2 1:0 Name Tim4CptEdg Tim4CptEvtSrc Tim4CmpFullAct Tim4CmpValAct
RegTim3Status Type ResVal RO 0x00 RegTim3Full Type ResVal RW 0xFF RegTim3CmpVal Type ResVal RW 0x00 RegTim3CptVal Type ResVal RO 0x00 RegTim4Cfg Type ResVal RW 0 RW 0 RW '000' RW '000' RegTim4CptCmpCfg Type RW RW RW RW ResVal '00' '00' '00' '00'
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys ResSys ResSys ResSys
ResSrc ResSys ResSys ResSys ResSys
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0x0051 Bits Name 7:0 Tim4Status 0x0052 Bits Name 7:0 Tim4Full 0x0053 Bits Name 7:0 Tim4CmpVal 0x0054 Bits Name 7:0 Tim4CptVal RegTim4Status Type ResVal RO 0x00 RegTim4Full Type ResVal RW 0xFF RegTim4CmpVal Type ResVal RW 0x00 RegTim4CptVal Type ResVal RO 0x00 ResSrc ResSys Timer4 Status Description Timer4 Status Timer4 Full / End Of Count value Description Timer4 Full / End Of Count value Timer4 Compare Value Description Timer4 Compare Value Timer4 Captured Value Description Timer4 Captured Value
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 18. SPI - SERIAL INTERFACE
The circuit contains a synchronous 3-wire (SDI, SDOUT and SCLK) master and slave serial interface. Its ports are mapped on different PA, PB and PC IO terminals. * SCLK: Serial Clock Input/ Output: Input in Slave mode, Output in Master mode * SDIN: Serial Interface Data Input. Input in Master and Slave mode * SDOUT: Serial Interface Data Output. Output in Master and Slave mode The serial interface always transmits or receives 8-bit packages at a time, followed by an interrupt request allowing the CPU to treat the data. An Interrupt IntSPIStart is generated at transmission start and an IntSPIStop at the end of the transmission. An Event EvtSPI is generated at transmission start and at the end of the transmission. The interface may also be used to generate a fix datastream output by using the Auto-Start mode. The internal shift register clock edge is user selectable; the interface may run on RTZ (Return To Zero) or RTO (Return to One) type of clocks The full SPI setup shall be configured before enabling the SPI (SPIEn='1'). Once enabled the configuration must not be changes anymore. While SPIEn is `0', SPIStart is reset. SPIEn must be written `1' before SPIStart is set. The transmission may start as soon as SPIStart is set `1'. Always make first full SPI setup and only at the end set the bit SPIStart to `1' to begin the data exchange. The register RegSPIDOut and RegSPIDIn act as a buffer for outgoing and incoming data. The RegSPIDOut must be th written before the transmission starts. The RegSPIDIn will be updated after the 8 active clock with the actual received input data. The transmission direction is configurable with bit SPIMSB1st. Set to `1' the first transmission bit is the MSB bit , if set `0' then it is the LSB bit. Figure 24, Serial Interface Architecture
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18.1 SCLK - SPI MASTER/ SLAVE MODE AND CLOCK SELECTION
Master and Slave mode as well as master mode clock selection are done in register RegSPICfg1 bits SPIMode. In Slave mode the serial input clock is coming from PA6, PB2 or PC6 input. The selection depends on SPISelSClk bits in register RegSPICfg2 and the corresponding port input enable bit must be `1'. SCLK Frequency selection SPIMode SCLK base clock SCLK Slave mode input selection Input Input condition terminal Slave Mode PA6 PB2 PC6 PA6 SPISelSClk='00' PA6InpE='1' SPISelSClk='01' PB2InpE='1' SPISelSClk='10' PC6InpE='1' SPISelSClk='11' PA6InpE='1' 000 (slave) 000 (slave) 000 (slave) 000 (slave)
SPIMode[2:0]
SLAVE Mode SCLK from port inputs 000 from PA6, PB2 PC6
Master mode, Prescaler 2 clocks 001 010 011 100 Ck_Hi Pr2Ck9 Pr2Ck8 Pr2Ck7
SCLK Master mode output selection Output Output condition terminal Master Mode PA6
Master mode, Prescaler 1 clocks 101 Ck_Lo
PA6OutSel[1:0]='01' PA6OE='1' PB2OutSel[1:0]='01' 110 Pr1Ck13 PB2 PB2OE='1' PC6OutSel[1:0]='01' 111 Pr1Ck12 PC6 PC6OE='1' The used PA, PB and PC IO port terminals must be set up for SPI before SPIStart is set high. Following table shows the different SCLK clock possibilities RTZ and RTO with the internal shift clock dependencies. SCLK IDLE Clock ShiftEdge Example on SCLK SPIRTO SPINegEdg SCLK pulse value type
0 0 1 1 0 1 0 1 High Pulse High Pulse Low pulse Low pulse High High Low Low Pos edge Neg edge Pos edge Neg edge RTZ RTZ RTO RTO
SPIRTO defines a RTZ clock type if set to `1' or RTO clock type if set to `0' SPINegEdg defines the internal shift register shift clock edge, set to `1' shift takes place on the negative SCLK clock edge. Set to `0', the shift will take on the positive SCLK clock edge. Both bits are placed in register RegSPICfg1.
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18.2 SIN PORT MAPPING
The serial data input may come from PA4, PB0 or PA2. On PA2 and PA4 the debounced signal PADeb2 or PADeb4 is used as serial data input, from PB0 it is directly the pad input while the input enable is high. The data shifted in through SIN terminal will be stored into the buffer register RegSPIDIn after the 8th shift clock. MSB or LSB first on the SIN reception is selected with bit SPIMSB1st. Input terminal PA4 PB0 PA2 PA4 Input condition SPISelSIN[1:0]='00' PA4InpE='1' SPISelSIN[1:0]='01' PB0InpE='1' SPISelSIN[1:0]='10' PA2InpE='1' SPISelSIN[1:0]='11' PA4InpE='1'
18.3 SOUT PORT MAPPING
The serial data output is mapped on PB4, PA2 or PC2. The corresponding port output must be setup by the corresponding port output selection bits as SDOUT output with its output enable high. The data to be shift out must be written into the output buffer register RegSPIDOut before the transmission is started. MSB or LSB first on the SOUT transmission is selected with bit SPIMSB1st. Output terminal PB4 PA2 PA7 PC2 Output condition PB4OutSel[1:0]='01' PB4OE='1' PA2OutSel[1:0]='01' PA2OE='1' PA7OutSel[1:0]='01' PA7OE='1' PC2OutSel[1:0]='01' PC2OE='1'
18.4 SPI START - STOP
In master mode writing bit SPIStart='1' will launch the transmission when it goes high and SPIEn='1'. After the 8th active SCLK clock edge the SPIStart will be forced low. SPISart can be used as a status register to momitor ongoing transmission. Writing `0' to SPIStart during the transmission will stop the SPI. In this case the content of RegSPIDIn is not guaranteed. Note: Chipselect handling for master mode shall be handled by the user software on any user defined PA, PB or PC output.
In slave mode, the transmission starts as soon as the 1st clock pulse occurs after SPIStart was written `1'. Note: In slave mode, for the synchronization, the user can generate a flag by software on a terminal to indicate to the master that the SPI is ready.
18.5 AUTO-START
With Auto-Start one can transmit several 8-bit packages without any delay between the packages. As such it allows generating a fix datastream output. The bit SPIAutoStart needs to be high to allow Auto-Start For Auto-Start to take place one needs to write the next package data into the RegSPIDOut during the ongoing transmission. The SPIStart will in this case stay high after the 8th active clock edge and the new transmission will follow immediately after. All interrupts IntSPIStart, IntSPIStop and the event EvtSPI are generated also in Auto-Start mode. If the bit SPIAutoStart is at `0', the auto start mode is be disabled, writing to RegSPIDOut during the transmission will have no effect.
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18.6 RTZ POSITIVE EDGE TRANSMISSION
With RTZ (Return To Zero) positive edge transmission the SCLK clock is low between successive transmissions. The SOUT data will change on the on the rising SCLK clock edge. The 1st bit of data SPIDout data will be shift out on the rising edge of the 1st SCLK clock and the last on the 8th SCLK clock rising edge. The SIN data must be stable at the SCLK rising edge to be properly shifted in, the buffer RegSPIDIn will be updated with the received data at the rising edge of the 8th shift clock. _____________________________________________________________________________________________ An interrupt request IntSPIStart and an event EvtSPI are generated by the rising edge of the 1st SCLK clock. An interrupt request IntSPIStop and an event EvtSPI are generated by the rising edge of the 8th SCLK clock. Figure 25, RTZ Positive edge transmission
18.7 RTO POSITIVE EDGE TRANSMISSION
With RTO (Return To One) positive edge transmission the SCLK clock is high between successive transmissions. The 1st bit contains in RegSPIDOut will be on SOUT before the first transmission if SPIEn = `1' or on the falling edge of the 7th SCLK pulse after the transmission. The 2nd bit contains in RegSPIDOut will be shifted out on the rising edge of the 1st SCLK pulse. The 8th bit contained in RegSPIDOut will be shifted out on the rising edge of the 7th SCLK pulse. SIN data must be stable on the rising edge of SCLK to be properly aquired and shifted. The buffer register RegSPIDIn will be updated with the received data on the rising edge of the 8th SCLK clock. An interrupt request IntSPIStart and an event EvtSPI are generated by the rising edge of the 1st SCLK clock. An interrupt request IntSPIStop and an event EvtSPI are generated by the rising edge of the 8th SCLK clock. Figure 26, RTO Positive edge transmission
_____________________________________________________________________________________________
18.8 RTZ NEGATIVE EDGE TRANSMISSION
With RTZ (Return To Zero) negative edge transmission the SCLK clock is low between successive transmissions. The 1st bit contains in RegSPIDOut will be on SOUT before the first transmission if SPIEn = `1' or on the falling edge of the 7th SCLK pulse after the transmission. The 2nd bit contains in RegSPIDOut will be shifted out on the falling edge of the 1st SCLK pulse. The 8th bit contains in RegSPIDOut will be shifted out on the falling edge of the 7th SCLK pulse. SIN data must be stable on the falling of SCLK to be properly aquired and shifted. The buffer register RegSPIDIn will be updated with the received data on the falling edge of the 8th SCLK clock. An interrupt request IntSPIStart and an event EvtSPI are generated by the falling edge of the 1st SCLK clock. An interrupt request IntSPIStop and an event EvtSPI are generated by the falling edge of the 8th SCLK clock. Figure 27, RTZ Negative edge transmission
_____________________________________________________________________________________________
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18.9 RTO NEGATIVE EDGE TRANSMISSION
With RTO (Return To One) negative edge transmission the SCLK clock is high between successive transmissions. The SOUT data will change on the on the falling SCLK clock edge. The 1st bit of data SPIDout data will be shift out on the falling edge of the 1st SCLK clock and the last on the 8th SCLK clock falling edge. The SIN data must be stable at the SCLK falling edge to be properly shifted in, the buffer RegSPIDIn will be updated with the received data at the falling edge of the 8th shift clock. An interrupt request IntSPIStart and an event EvtSPI are generated by the falling edge of the 1st SCLK clock. An interrupt request IntSPIStop and an event EvtSPI are generated by the falling edge of the 8th SCLK clock. Figure 28, RTO Negative edge transmission
Note: The SPI signals has the following setup and hold time parameters: Conditions: VSUP = 2.0 V, Temp = -40C to 85C, external Cload on pad = 30 pF max 8 MHz SCLK frequency, port A and C fSPIAC max 10 MHz SCLK frequency, port B fSPIB min 6 ns SIN setup time, slave mode tsuSINS min 29 ns (portA,C), min 25ns (port B) SIN setup time, master mode tsuSINM min 5 ns SIN hold time thdSIN max 32ns (port A, C), max 26ns (port B) SOUT delay_time TdelSOUT Above values are not verified on production testing.
18.10
SPI REGISTERS
RegSPICfg1 Type ResVal RW 0 RW '000' RW 0 RW 0 RW 1 RW 1 RegSPICfg2 Type ResVal RW '00' RW '00' NI RegSPIStart Type ResVal STS 0 NI RegSPIDIn Type ResVal RO 0x00 RegSPIDOut Type ResVal RW 0x00 ResSrc ResSys ResSys ResSys ResSys ResSys ResSys SPI Configuration - 1 Description SPI Enable SPI Mode and SClk selection SPI active on Negative Edge SPI RTO (Return To One) SPI MSB First SPI Auto Start Enabled SPI Configuration - 2 Description SPI SClk Selection SPI SIn Selection Not implemented SPI Start Description SPI Start Not implemented SPI Received Data Description SPI Received Data SPI Data to Transmit Description SPI Data to Transmit
0x007A Bits Name 7 SPIEn 6:4 SPIMode 3 SPINegEdg 2 SPIRTO 1 SPIMSB1st 0 SPIAutoStart 0x007B Bits Name 7:6 SPISelSClk 5:4 SPISelSIn 3:0 0x007C Bits Name 7 SPIStart 6:0 0x007D Bits Name 7:0 SPIDIn 0x007E Bits Name 7:0 SPIDOut
ResSrc ResSys ResSys -
ResSrc ResSys -
ResSrc ResSys
ResSrc ResSys
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The function of the watchdog is to generate a reset ResSys and ResAna by asserting the ResWD signal if during a given timeout period the CPU did not clear the WD counter (WDClear). It therefore uses a 16-bits counter that counts down from start (RegWDLdValM (MSB) and RegWDLdValL (LSB)) value down to 0x0000. The counter uses directly the RC 8 KHz clock. This RC clock is always enabled together with the watchdog. Refer also to chapter Oscillator and Clock selection for the RC 8 KHz clock. Figure 29, Watchdog architecture
19.1 WATCHDOG CLEAR
The software writes `1' to the one shot register RegWDCfg bit WDClear to avoid watchdog reset, at the same time the counter will reload the initial start value given by registers RegWDLdValM and RegWDLdValL. If the counter reaches 0x0000 and WDDis = `0' then signal WatchDog timeout ResWD will be asserted. The watchdog counter status can be read in registers RegWDStatM (MSB) and RegWDStatL (LSB). Note: Due to asynchronous domain crossing the SW may read the status during its change i.e. a nonsense value. Only two consecutive reads of the same stable value can assure about its correctness if the WD is running. The occurrence of a watchdog reset can be read in the rest flag register RegResFlag bit ResFlagWD. The timeout, based on the 8 KHz RC oscillator can be set as high as 8.2s (load value of 0xFFFF) with a LSB value of typical 125us. The default load value of 0x8000 corresponds to 4.1 secondes. In sleep mode watchdog is always disable.
19.2 WATCHDOG DISABLING
If the register RegWDKey contains the value (watch_dog_key = 0xCA) it becomes possible to disable the WD by writing `1' to register RegWDCfg bit WDDis. If RegWDKey contains the watchdog a value <> 0xCA it will be impossible to disable the WD, register RegWDCfg bit WDDis will be forced low. The WatchDog counter is disabled in Sleep mode and if RegWDCfg.WDDis = `1' while watch_dog_key is valid. The counter will reload the start value when started and/or re-enabled. Note: The WatchDog Clear may take up to 3 WD clocks (~375 us). The WatchDog Start-up may take up to 4 WD clocks (~500 us). Any change in RegWdLdValM or RegWdLdValL during this time will affect the WD Counter value.
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19.3 WATCHDOG REGISTERS
0x0006 Bits Name 7 ResFlgPA 6 ResFlgWD 5 ResFlgBO 4 ResFlgGasp 3 ResFlgBE 0 LckPwrCfg 0x006D Bits Name 7 WDDis 0 WDClear 0x006E Bits Name 7:0 WDKey 0x006F Bits Name 7:0 WDLdValL 0x0070 Bits Name 7:0 WDLdValM 0x0071 Bits Name 7:0 WDStatL 0x0072 Bits Name 7:0 WDStatM RegResFlg Type ResVal ResFlg 0 ResFlg 0 ResFlg 0 ResFlg 0 ResFlg 0 RW 0 RegWDCfg Type ResVal RW 0 OS 0 RegWDKey Type ResVal RW 0x00 RegWDLdValL Type ResVal RW 0x00 RegWDLdValM Type ResVal RW 0x80 RegWDStatL Type ResVal RO 0x00 RegWDStatM Type ResVal RO 0x80 ResSrc PorLog PorLog PorLog PorLog PorLog Por Reset Flags Description Flag Reset from Port-A Flag Reset from WatchDog Flag Reset from Brown-Out Flag Reset from GASP Flag Reset from CoolRisc Bus-Error Lock configurations to be kept in Power-Down mode WatchDog Configuration Description WatchDog Disable WatchDog Clear - Restart Counting WatchDog Key (0xCA) for disabling Description WatchDog Key (0xCA) for disabling WatchDog Start/Load value LSB Description WatchDog Start/Load value LSB WatchDog Start/Load value MSB Description WatchDog Start/Load value MSB WatchDog Status LSB Description WatchDog Status LSB WatchDog Status MSB Description WatchDog Status MSB
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
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The SC wake-up function generates a timeout which may be used as a sleep wake-up or as an asynchronous interrupt or event generation timer in active or standby mode. The max delay is 35min, programmable in 125us steps. When the timeout is reached an interrupt IntSlpCnt or event EvtSlpCnt will be asserted. If the circuit was in sleep mode the interrupt or event will wake it up and software execution will start, if the circuit was in active or standby mode it will interpret the interrupts or events excecute the instruction code. In order to wake-up from sleep or to see the interrupt or event the corresponding interrupt and event must not be masked. The SCWU uses a 24-bit counter down counter running on the internal RC 8 KHz oscillator. Figure 30, Sleep wake-up counter architecture
The counter state shall be readable by registers RegSCStat2 (MSB), RegSCStat1 and RegSCStat0. Note: Due to asynchronous domain crossing the SW may read the status during its change i.e. a nonsense value. Only two consecutive reads of the same stable value can assure about its correctness if the SC is running. Note: As sleep counter is a state machine running at low frequency, two consecutive actions from CPU on sleep-counter as stop or start shall be separated by at least 2.5 ms delay. Once the counter reaches 0x000000 value then IntSlpCnt and EvtSlpCnt will be asserted regardless of the mode. The counting is stopped.
20.1 SC WAKE-UP ENABLING
The counter can only start when SCDis='0' (enabled). If SCDis = `0' the counter starts automatically when system enters in sleep mode. When the counter starts it will first load the RegSCLdVal2,1,0 and then downcount from the loaded value. The current counter value can be read in the status registers RegSCStat2,1,0. The default load value is 0x008000 which corresponds to a timeout of 4.1s. An active SC wake-up will automatically switch on the internal RC 8 kHz oscillator. SCStart can be used to trim the SC in active mode. Charge sharing effects influence the SCWKUP timing slightly when going into Sleep mode. Resulting timings are therefore up to 2.2ms longer than expected. Note: SCStart shall not be set to `1' before going in sleep mode it shall be used only in active mode to trim the sleep counter wake-up delay.
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20.2 SC WAKE-UP DISABLING
If SCDis = `1' the counter will be disabled regardless of the mode. The counter will stop when SCStart is set to `0' or after Sleep mode wake-up. Once stopped, the counter will keep its current value. The SC wake-up function is reset by ResSys. Note: Due to asynchronous domain crossing the reload and following start takes 2-3 SC clocks (~250-375 us). Note: If in sleep mode system is woke-up by another source as SC wake-up (by PortA) before SC reaches 0x000000 then the SC needs 2-3 clocks cycle before stopping. If system enter again in sleep mode before proper SC stop, SC do not reload RegSCLdVAl2,1,0 then SC delay is shorter than expected.
20.3 SC WAKE-UP REGISTERS
0x0073 Bits Name 7 SCDis 6 SCStart 5:0 0x0074 Bits Name 7:0 SCLdVal0 0x0075 Bits Name 7:0 SCLdVal1 0x0076 Bits Name 7:0 SCLdVal2 0x0077 Bits Name 7:0 SCStat0 0x0078 Bits Name 7:0 SCStat1 0x0079 Bits Name 7:0 SCStat2 RegSCCfg Type RW RW NI ResVal 0 0 ResSrc ResSys ResSys SleepCounter Configuration Description SleepCounter Disable SleepCounter Start/Run Not implemented SleepCounter Start/Load value B0-LSB Description SleepCounter Start/Load value B0-LSB SleepCounter Start/Load value B1 Description SleepCounter Start/Load value B1 SleepCounter Start/Load value B2-MSB Description SleepCounter Start/Load value B2-MSB SleepCounter Status B0-LSB Description SleepCounter Status Byte0-LSB SleepCounter Status B1 Description SleepCounter Status Byte1 SleepCounter Status B2-MSB Description SleepCounter Status Byte2-MSB
RegSCLdVal0 Type ResVal RW 0x00 RegSCLdVal1 Type ResVal RW 0x80 RegSCLdVal2 Type ResVal RW 0x00 RegSCStat0 Type ResVal RO 0x00 RegSCStat1 Type ResVal RO 0x80 RegSCStat2 Type ResVal RO 0x00
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
ResSrc ResSys
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Two blocks compose the ADC: * The conditioner * The ADC converter The conditioner allows sampling different range of analog inputs even signal having a dynamic higher than VSUP. It consists to decrease the reference and the analog input in a range adapted for the ADC converter.
21.1 CONDITIONER
21.1.1 RANGE SELECTION
It consists to attenuate the external analog input range and external reference. It is used to adapt external range to internal range limited to maximum 1.7V as illustrated in the following diagram.
Vref_ext max
Maximum external range
Vref_ext min
Minimum external range
Vref_int max Vref_int min
Minimum internal range Maximum internal range
vss
Vref_ext max: Maximum external range Vref_ext min: Minimum external range Vref_int max: Maximum internal range = 1.7V Vref_int min: Minimum internal range = 1.1V
External reference and attenuation factor called range shall be calculated to get an internal refenrence in a window of 1.1V to 1.7V. There is another condition to fullfil; the maximum external reference shall not be above VSUP if VSUP > VREG. If VSUP < VREG the maximum external reference is 1.7V. There are 4 possible ranges. The factor shall be chosen to get an internal reference in the window of 1.1V to 1.7V according to the following table: Range 8/8 6/8 4/8 3/8 Vref_ext min 1.10 V 1.47 V 2.20 V 2.93 V Vref_ext max 1.70 V 2.27 V 3.40 V 3.60 V (1)
(1) The maximum external range is limitated by maximum power supply 3.6V
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External - internal references relation with 8/8 range
External reference window
1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.9 1.8 1.7 1.6 1.5 1.4 1.3
External - internal references relation with 6/8 range
External reference window
1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 3.2 3.4 3.6 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Vref_int [V]
Vref_int [V]
1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 3.2 3.4 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.6 3.6
8/ 8
e ng ra
ra
8 6/
ng e
Vref_ext [V]
Vref_ext [V] External - internal references relation with 3/8 range
External reference window
1.9 1.8 1.7
External - internal references relation with 4/8 range
External reference window
1.9 1.8
Internal reference window
1.6 1.5 1.4 1.3
Vref_int [V]
Vref_int [V]
1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 3.2 3.4 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.6
1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 3.2 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.4
ge ran
4/8
ge ran
3/8
Vref_ext [V]
Vref_ext [V]
The selection of the attenuation factor is done with ADCSelRange[1:0] in the register RegADCCfg2[5:4]. ADCSelRange[1:0] 00 01 10 11 Attenuation factor 8/8 6/8 4/8 3/8
21.1.2 REFERENCE SELECTION
There are three different possible references selectable with ADCSelRef[1:0] in the register RegADCCfg2[7:6]. ADCSelRef[1:0] 00 01 10 11 reference VBGR VREF_EXT VSUP unused origin Internal reference PA2 Main supply VSUP -
When external reference VREF_EXT is used, PA[2] shall be configured in analog mode: RegPAOE[2] = `0', RegPAInpE[2] = `0', RegPAPU[2] = `0' and RegPAPD[2] = `0'.
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Internal reference window
1.7 1.6 1.5 1.4
Internal reference window
Internal reference window
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Note: Always allow the reference voltage to stabilize before starting an ADC measure. When running on the internal reference this stabilization time is 130us from ADCEn until stable reference voltage. It is possible to start the reference prior to enabling of the ADC, refer to 24.
21.1.3 ANALOG INPUT SELECTION
There are 9 possible analog inputs selectable with ADCSelSrc[2:0] in register ADCOut1[6:4]. When the temperature sensor is active (EnTempSens in register RegADCCfg1[4] = `1') the temperature sensor is automatically set as ADC analog input. StsTempSens in register RegADCOut1[3] is a copy of EnTempSens and is not writable. It allows checking if the temperature sensor is enable at each read of ADC data output. EnTempSens 0 0 0 0 0 0 0 0 1 ADCSelSrc[2:0] 000 001 010 011 100 101 110 111 xxx ADC source PA0 PC0 PA1 PC1 PA2 PC2 PA3 PC3 temperature sensor
21.2 ADC OFFSET TRIM SELECTION
Depending on the ADC configuration or if the ADC is used with the temperature sensor, the ADC offset shall be set differently. When the internal voltage is used, the ADC range selection has effect only on the analog input signal. Then the offset has to be adapted to the selected range. There is also a dedicated offset trim word used when the analog input is the temperature sensor in order to remove the offset error introduced by the sensor itself. All these trimming words are contained in the row 62 sector 5 of the NVM (refer to the chapter 3.6). The offset trim to use according to the configuration is as follows: ADC configuration ADC ref = internal Vref Range 3/8 ADC ref = internal Vref Range 4/8 ADC ref = internal Vref Range 6/8 Temperature sensor All other configurations ADC offset trim ADCOffsetRng3_8[10:0] ADCOffsetRng4_8[10:0] ADCOffsetRng6_8[10:0] ADCOffsetTemp[10:0] ADCOffsetRng8_8[10:0] DM address MSB 0x6FD1[10:8] LSB 0x6FD0[7:0] MSB 0x6FCF[10:8] LSB 0x6FCE[7:0] MSB 0x6FCD[10:8] LSB 0x6FCC[7:0] MSB 0x6FC9[10:8] LSB 0x6FC8[7:0] MSB 0x6FCB[10:8] LSB 0x6FCA[7:0]
The trimming word has to be copied from the NVM to the related registers: MSB in RegADCOffsetM DM address 0x005A and LSB in RegADCOffsetL DM address 0x0059. Note: ADC offset is coded and memorized in NVM on 11 bits. Their value can be above 0x3FF.
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ADC configurations
21.2.1 RUNNING MODE
The 6819 ADC has two possible running modes: * Continuous mode: the ADC runs continuously until the software stopps it. * One shot mode: the ADC makes just one single acquisition. To start the ADC in continuous mode, RunContMeas in register RegADCCfg1[6] shall be set at `1'. To start a single sample, RunSinglMeas in register RegADCCfg1[5] shall be set at `1'. Continuous mode has the priority over single measurement. Always fully define the ADC setup before starting any ADC measurement.
21.2.2 ADC ENABLING
Before to start an acquisition, EnADC in register RegADCCfg1[7] shall be set at `1'. When the ADC is stopped in continuous mode, EnADC shall be set at `0' before to launch any other acquisition otherwise all next measurement will be corrupted. Note: EnADC will also enable the bandgap reference voltage. If the BGR is used as ADC reference the user must wait for the BGR to stabilize before starting any measurement. Refer to 24. If an external reference is used or the BGR was already enabled before - and is stabilized - still allow 5us setup time from EnADC to start of measuring.
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21.2.3 ADC SAMPLING RATE
The ADC can select 8 different sampling rates. ADC is running on Ck_Hi whatever the clock configuration. When the CPU and the Prescalers are not running on Ck_Hi, the clock for ADC shall be forced. Meaning that FrcEnRC15M or FrcEnRC2M or FrcEnExt shall be forced at `1' and Ck_Hi shall be connected to the clock source forced. The maximum sampling rate of the ADC is 100kS/s, the ADC needs 22 clocks for each sample, than the maximum selectable ADC frequency is 2.2MHz. The clock selection is done with ADCSmplRate[2:0] in register RegADCCfg1[3:1]. Following table shows the relation between the clock source selection and the sampling rate. ADCSmplRate[2:0] 000 001 010 011 100 101 110 111 Clock division factor 1 (default) 2 4 8 16 32 64 1 Sampling rate kS/s Ck_Hi = 2MHz 90.91 45.45 22.73 11.36 5.68 2.84 1.42 90.91
Ck_Hi = 15MHz denied denied denied 83.78 41.89 20.95 10.47 denied
Ck_Hi = 4MHz Xtal denied 90.91 45.45 22.73 11.36 5.68 2.84 denied
The first conversion shall be ignored. Then in single mode the conversion need 44 clocks. This is automatically managed by the 6819, the event is generated only after the second conversion. Following table shows the relation between the conversion duration and the clock source selection. ADCSmplRate[2:0] 000 001 010 011 100 101 110 111 Clock division factor 1 (default) 2 4 8 16 32 64 1 Conversion duration us Ck_Hi = 2MHz Ck_Hi = 4MHz Xtal 22.00 denied 44.00 22.00 88.00 44.00 176.00 88.00 352.00 176.00 704.00 352.00 1408.00 704.00 22.00 denied
Ck_Hi = 15MHz denied denied denied 23.87 47.74 95.49 190.97 denied
21.2.4 LOW NOISE MODE
There is two way to decrease the noise due to activity of 6819: * Force DC-DC in idle mode for a short time. * Make ADC acquisition only when the CPU is in halt mode. When the DC-DC is used, it is possible to stop it for a short time by setting DC-DCIdle in register RegDC-DCCfg[4] at `1'. In this case the only source of energy is the external capacitor. Then it is recommended to ensure that no big consumer is working when the DC-DC is in idle mode (refer to DC-DC chapter). As soon as the ADC convertion is done the DCDIdle shall be set at `0' again. The ADC should be used only in one shot mode in this case to recharge the external capacitor between between each ADC acquisition. ADC low noise mode consists to start the ADC convertion only when the CPU is in stand by mode by setting ADCLowNoise in register RegADCCfg2[3] at `1'. The CPU is waked up by ADC event or ADC interrupt when the convertion is done and ADC result available if they are unmasked.
21.2.5 8BIT ADC SELECTION
It is possible to set the size of the ADC result between 10 or 8-bits. If high precision is not required, it allows simplifying the software as the data are in 8bit. In this case two LSB bits are lost. The other bits are shifted in register RegADCOut0[7:0]. In 10-bits mode the result is split in registers RegADCOut1[1:0] (2 MSB bits) and RegADCOut0[7:0] (8 LSB bits).
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21.3 ADC ACQUISITION SEQUENCE
The ADC generates an interrupt or an event when the acquisition is done and the result available for CPU. Thank to the event it is possible to force the CPU in std-by mode, the event wake-up the CPU automatically when the ADC result is available. It allows in continuous saving time because the CPU does not need to go through the handler. It is also possible to react by polling the event with conditional jump JEV. Int0StsADC in register RegInt0Sts[4] is the interrupt generated at the end of each acquisition. Evt1StsADC in register RegEvtSts[1] is the event generated at the end of each acquisition. The ADC result is available in registers RegADCOut1[1:0] (2 MSB bits) and RegADCOut0[7:0] (8 LSB bits). To ensure that a new acquisition between reading RegADCOut1[1:0] and RegADCOut0[7:0] does not corrupt the ADC result, RegADCOut0[7:0] is stored in a shadow register when RegADCOut1[1:0] is read. Both registes are read in fact exactly in the same time. RegADCOut1[1:0] shall always be read first.
th RegADCOut1.ADCOutLSB is the 11 bits result LSB and it is not guaranteed.
The bit ADCBusy in read-only register RegADCOut1[7] is at `1' when the ADC is working. It allows detecting the end of acquisition in one shot mode by polling.
21.4 ADC REGISTERS
0x0055 Bits Name 7 EnADC 6 RunContMeas 5 RunSinglMeas 4 EnTempSens 3:1 ADCSmplRate 0 ADC8bit 0x0056 Bits Name 7:6 ADCSelRef 5:4 ADCSelRange 3 ADCLowNoise 2:0 0x0057 Bits Name 7:0 ADCOut0 0x0058 Bits Name 7 ADCBusy 6:4 ADCSelSrc 3 StsTempSens 2 ADCOutLSB 1:0 ADCOut1 0x0059 Bits Name 7:0 ADCOffsetL 0x005A Bits Name 7:3 2:0 ADCOffsetM RegADCCfg1 Type ResVal RW 0 RW 0 STS 0 RW 0 RW '000' RW 0 RegADCCfg2 Type ResVal RW '00' RW '00' RW 0 NI RegADCOut0 Type ResVal RO 0x00 RegADCOut1 Type ResVal RO 0 RW '000' RO 0 RO 0 RO '00' RegADCOffsetL Type ResVal RW 0x00 RegADCOffsetM Type ResVal NI RW '100' ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ADC Configuration - 1 Description Enable ADC Block Run Continues measurement Run/Start Single measurement Enable Temperature Sensor ADC Sample Rate setup - continues mode. ADC 8bit Result mode ADC Configuration - 2 Description ADC Reference selection ADC Range selection ADC Low noise measurement mode Not implemented ADC Output-0 (LSB) Description ADC Output-0: 10bit=LSB(8:1), 8bit-(10:3) ADC Output-1 (MSB) Description ADC in progress ADC Input Source selection Enable Temperature Sensor Status ADC Output HW-LSB(0) ADC Output-1: 10bit-MSB(10:9), 8bit-N/A ADC Offset LSB (7:0) Description ADC Offset LSB (7:0) ADC Offset MSB (10:8) Description Not implemented ADC Offset MSB (10:8)
ResSrc ResSys ResSys ResSys -
ResSrc ResSys
ResSrc ResSys ResSys ResSys ResSys ResSys
ResSrc ResSys
ResSrc ResSys
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22.1 TEMPERATURE SENSOR ENABLING
The temperature sensor is enabled when EnTempSens in register RegADCCfg1 is written at `1'. When the temperature sensor is enabled it is automatically selected by the ADC as input source. Read-only bit StsTempSens in register RegADCOut1 is a copy of EnTempSens. Thank to it the status of temperature sensor is given on each ADC result read access.
22.2 TEMPERATURE SENSOR REGISTERS
0x0055 Bits Name 7 EnADC 6 RunContMeas 5 RunSinglMeas 4 EnTempSens 3:1 ADCSmplRate 0 ADC8bit 0x0058 Bits Name 7 ADCBusy 6:4 ADCSelSrc 3 StsTempSens 2 ADCOutLSB 1:0 ADCOut1 RegADCCfg1 Type ResVal RW 0 RW 0 STS 0 RW 0 RW '000' RW 0 RegADCOut1 Type ResVal RO 0 RW '000' RO 0 RO 0 RO '00' ResSrc ResSys ResSys ResSys ResSys ResSys ResSys ADC Configuration - 1 Description Enable ADC Block Run Continues measurement Run/Start Single measurement Enable Temperature Sensor ADC Sample Rate setup - continues mode. ADC 8bit Result mode ADC Output-1 (MSB) Description ADC in progress ADC Input Source selection Enable Temperature Sensor Status ADC Output HW-LSB(0) ADC Output-1: 10bit-MSB(10:9), 8bit-N/A
ResSrc ResSys ResSys ResSys ResSys ResSys
Note: Temperature sensor calibration values are stored in row 62 sector 5 as described in chapter 4.6. Temperature tolerances of production test are described in chapter 4.6.1. When EnTempSens is written at `1' it is necessary to wait 10ms before to launch an ADC acquisition.
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The DC-DC converter allows supplying the chip and external elements on the board using a low voltage supply source. The DC-DC converter is not enabled by default but by the software. 6819 is able to start-up with a low voltage supply using the internal voltage multiplier. As the voltage multiplier is not able to deliver more than 100uA, it is recommended to enable the DC-DC before to enable the big consumers.
23.1 DC/DC ENABLING
Enable the DC-DC consists to write `1' in EnDC-DC in register RegDC-DCCfg[7]. During the start-up phase of DC-DC the read-only bit DC-DCStartSts in RegDC-DCCfg[3] is at `1'. The current driven shall not exceed 10mA during the start-up phase.
23.2 DC/DC VOLTAGE SELECTION
There are 4 target voltages selectable with DC-DCLevel[1:0] in register RegDC-DCCfg[6:5]. It is possible to change the voltage level of DC-DC on the fly while DC-DC is enabled but when the voltage rise up the current driven shall not exceed 10mA. DC-DCLevel[1:0] Voltage level 0x00 2.1 0x01 2.5 0x10 2.9 0x11 3.3
23.3 DC/DC LOW NOISE MODE
The noise level generated by the DC-DC converter can possibly influence precise voltage monitoring on VLD and ADC. To avoid such noise influence the DC-DC converter can be put in IDLE mode during such measurements. The IDLE duration is purely software controlled. Writing `1' in DC-DCIdle in register RegDC-DCCfg[4] force the DC-DC off, in this mode the external capacitance becomes the only source of energy. Then the big consumer shall be switched off when DC-DCIdle is set to `1'. It is recommended to use the VLD to supervise VSUP and switch the DC-DC on when the supply is to low. The time the DC-DC can be in idle is related to the maximum voltage drop on VSUP, the external capacitor value and the current consumption as follows. Delay in idle mode TDC-DCIdle: C VSUP External capacitor value Cext: TDCDCIdle = EXT VSUP: Drop on VSUP I SUP ISUP: Current consumption on VSUP
Note: The DC-DC - Step-Up converter does not allow Voltage down conversion.
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23.4 DC-DC REGISTER
Bits 7 6:5 4 3 2:0 0x005D Name EnDC-DC DC-DCLevel DC-DCIdle DC-DCStartSts RegDC-DCCfg Type ResVal ResSrc RW 0 ResAna RW '00' ResAna RW 0 ResAna RO 0 NI DC-DC Configuration Description Enable DC-DC Select DC-DC Output Level DC-DC Idle mode DC-DC Start-up status Not implemented
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 24. BAND GAP
The band gap voltage reference, written also BGR in this document, generates the reference voltage used for the following peripherals: * VLD (while VLD enabled) * ADC, (while ADC enabled CPU in active or standby mode) * DC-DC, (while DCDC enabled) * OPAMP (while OPAMP enabled and the BGR or the VLD reference is selected as one of the OPAMP inputs * BGR output on PA[6], (while the reference voltage is output) * NVM memory modification (fully controlled by ROM-API) First time enabled allow for 130us reference voltage stabilization time before using one of the above mention functions needing the BGR voltage. The reference voltage is automatically enabled as soon as one of the above mentioned functions is enabled. The reference voltage can be forced on by writing the bit NVMEnWrite in register RegBgrCfg[6] to `1' prior to use it for destination function. This allows using the VLD and ADC immediately after enabling (no need to wait first for BGR stabilization).
The BGR can be used as an external reference as well. Writing `1' in BgrEnOut in register RegBgrCfg[7] connects the voltage reference to PA[6] that shall be configured as analog pad before (digital output and input mode off and no pull's).
24.1 BAND GAP REGISTER
0x0060 Bits Name 7 BgrEnOut 6 NVMEnWrite 5:0 RegBgrCfg Type ResVal RW 0 RW 0 NI ResSrc ResSys ResSys BandGap reference configuration Description Enable BandGap reference output to Port Enables BandGap in active mode Not implemented
Note: When connecting the reference voltage to the PA[6] output , the reference voltage may drop during the switching transition due to charge sharing from the internal reference voltage node to the external PA[6] pad and its attached capacitance. In this case the settling time can be longer than 130us. Always use the reference voltage only once it is completely stabilized.
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 25. VLD
The Voltage Level Detector (VLD) compares a voltage on a terminal pad to a fix reference and returns the result `1' or generates an interrupt if the voltage is below the reference. The measurement is static meaning that there is no need to start any sequence and the selected voltage source terminal is continuously supervised. The reference voltage VVLD is factory pretrimmed.
25.1 VLD SOURCE AND LEVEL SELECTION
There are 8 terminals selectable with VLDSelSrc[2:0] in register RegVLDCfg1[5:3] as follows: VLDSelSrc[2:0] 000 001 010 011 100 101 110 111 Source VSUP (default) PA1 PA2 PC1 PC5 PA6 PC6 PA7
The are 32 target level selectable with VLDSelLev[4:0] in register RegVLDCfg2[4:0] as follows: Refer to the electricalspecification for the voltage levels (spread from 0.8V to 3.0V) VLDSelLev[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Level VLD0 VLD1 VLD2 VLD3 VLD4 VLD5 VLD6 VLD7 VLD8 VLD9 VLD10 VLD11 VLD12 VLD13 VLD14 VLD15 VLDSelLev[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Level [V] VLD16 VLD17 VLD18 VLD19 VLD20 VLD21 VLD22 VLD23 VLD24 VLD25 VLD26 VLD27 VLD28 VLD29 VLD30 VLD31
25.2 VLD ENABLE
VLD is enable writing `1' in EnVLD in register RegVLDCfg1[7]. After enabling it is recommended to wait 150us before enabling the related interrupt or read the VLD result to allow the reference voltage to stabilize. This stabilization wait is only needed if the internal BGR voltage was not enabled for 150us prior to enabling the VLD. If the BGR was already enabled before still allow 20us for the VLD reference to stabilize after VLD enabling. Refer also to 24.
25.3 VLD RESULT
When the voltage measured is below the VLD level the read-only bit VLDRes in register RegVLDCfg1[6] is at `1'.
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25.4 VLD INTERRUPT
An interrupt is generated when the voltage measured is below the VLD level. The VLD interrupt IntSts2Vld is in register RegInt2Sts[7].
25.5 VLD TRIMMING
The VLD reference voltage VVLD is trimmed in production independently of the BGR. The trimming value is stored in the NVM at the address 0x6FF9. During the boot ROM sequence this value is copied in TrimVLD[3:0] in register RegTrimVLD. The user can modify this register to move slightly all VLD levels.
25.6 VLD REGISTERS
0x005E Bits Name 7 EnVLD 6 VLDRes 5:3 VLDSelSrc 2:0 0x005F Bits Name 7:5 4:0 VLDSelLev 0x02A4 Bits Name 7:4 3:0 TrimVLD RegVLDCfg1 Type ResVal RW 0 RO 0 RW '000' NI RegVLDCfg2 Type ResVal NI RW 0x00 RegTrimVLD Type ResVal NI RW 0x8 ResSrc ResSys ResSys ResSys VLD Configuration - 1 Description Enable VLD VLD Result/Output Select VLD Input/Source Not implemented VLD Configuration - 2 Description Not implemented Select VLD Level Trimming value for VLD Description Not implemented Trimming value for VLD
ResSrc ResSys
ResSrc ResAna
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 26. RC OSCILLATOR
There are 2 main internal RC oscillators: * 15MHz oscillator (runs at 14.7456 MHz but called 15MHz oscillator) * 2MHz oscillator Thes 2 oscillators are factory pretrimmed, the trim value is stored in the NVM at the following addresses: * 15MHz oscillator: 0x6FFD * 2MHz oscillator: 0x6FFC The boot ROM sequence copies the 15MHz trimming value from the NVM into TrimOsc15M in register RegTrimOsc15M and the 2MHz trimming value from the NVM into TrimOsc2M in register RegTrimOsc2M. The user can modify these two trimming in their destination register RegTrimOsc15M, RegTrimOsc2M. Note: Before any CALL of sub-routine erasing or writing the NVM, the default RC timming values from NVM shall be restored.
26.1 RC OSCILLATORS REGISTERS
0x02A2 Bits Name 7:0 TrimOsc15M 0x02A3 Bits Name 7:0 TrimOsc2M RegTrimOsc15M Type ResVal RW 0x80 RegTrimOsc2M Type ResVal RW 0x80 ResSrc ResAna Trimming value for the 15 MHz Oscillator Description Trimming value for the 15 MHz Oscillator Trimming value for the 2 MHz Oscillator Description Trimming value for the 2 MHz Oscillator
ResSrc ResAna
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 27. XTAL OSCILLATOR 32KHZ
XTAL oscillator is connected to the terminal pads PA4 (XIN) and PC4 (XOUT). These two pads shall be configured in analog mode (output and input mode disable and no pull's) before to launch the XTAL oscillator. Note: The XTAL oscillator shall be located as close as possible to the 6819. Both wires XIN and XOUT shall be routed as short as possible on the board. For all information concerning the different configuration related to the 32 KHz XTAL oscillator, refer to the chapter "Oscillator and Clocking structure".
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 28. RESONATOR 4MHZ
RC resonator is connected to the terminal pads PA4 (XIN) and PC4 (XOUT). These two pads shall be configured in analog mode (output and input mode disable and no pull's) before to launch the resonator. Note: The Resonator shall be located as close as possible to the 6819. Both wires XIN and XOUT shall be routed as short as possible on the board. Two capacitors of 39pF shall be implemented on the board. The first between XIN and VSS, the second between XOUT and VSS as describe in the following schematic:
XIN
XOUT
Ls Rs 39pF Cp Cs 39pF
For all information concerning the different configuration related to the 4MHz resonator, refer to the chapter "Oscillator and Clocking structure".
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 29. 8KHZ OSCILLATOR
The 8kHz oscillator is used mainly for the watch-dog and the sleep counter wake-up system. Its frequency is not trimmable. However timings generated by the 8kHz oscillator can be calibrated with the trimmed 2Mhz or 15Mhz oscillator. For very low power applications it is also possible possible to use the 8kHz oscillator for the CPU and the prescalers For all information concerning the different configuration related to the 8kHz oscillator, refer to the chapter "Oscillator and Clocking structure".
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 30. ANALOG OPAMP
Each pin of the OPAMP in 6819 can be connected to different terminal or other peripherals. The positive input selection is done with OpAmpSelInpPos[1:0] in register RegOpAmpCfg2[7:0] as following: OpAmpSelInpPos[1:0] positive input 00 PA3 01 PC3 10 VBGR 11 VVLD The negative input selection is done with OpAmpSelInpNeg[1:0] in register RegOpAmpCfg[7:0] as following: OpAmpSelInpNeg[1:0] negative input 00 PA2 01 PC2 10 VBGR 11 VVLD When the OPAMP is enable and comparator disable, the output can be mapped on to different terminal with OpAmpSelOut in register RegOpAmpCfg[3] as follows: OpAmpSelOut 0 1 output PA1 PC1
30.1 SELECT OPAMP/COMPARATOR
To enable the OPAMP, EnOpAmp in register RegOpAmpCfg1[7] shall be set at `1'. In this case the selected terminals are connected to the OPAMP. The terminal shall be configure in analog mode before to enable the OPAMP, it is not done automatically (output and input mode disable and no pull's). To enable the comparator EnOpAmp in register RegOpAmpCfg1[7] and EnComp in register RegOpAmpCfg1[6] shall set at `1'. In this mode the output is not mapped on any of the two terminals PA1 or PC1.
30.2 SUPPLY SELECTION
The OPAMP and the comparator are able to work under VREG or VSUP voltage to be able to select two different swings. Even when 6819 is supplied at 0.9V it is possible to get a swing of 1.6V if the OPAMP is supplied by VREG. When OpAmpSup in register RegOpAmpCfg1 is at `0' VSUP is selected, if it is at `1' VREG is selected.
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30.3 COMPARATOR RESULT
The comparator result is mapped on the read-only bit CompRes in register RegOpAmpCfg1[4]. The comparator can generate an interrupt mapped on Int1StsOpAmp in register RegInt1Sts[3]. It is possible to set on which edge the interrupt is generated with SelCompInt[1:0] in register RegOpAmpCfg1[3:2] as follows: SelCompInt[1:0] 00 01 10 11 interrupt generation no interrupt interrupt on rising edge interrupt on falling edge interrupt on both edges
30.4 OPAMP REGISTERS
0x005B Bits Name 7 EnOpAmp 6 EnComp 5 OpAmpSup 4 CompRes 3:2 SelCompInt 1:0 0x005C Bits Name 7:6 OpAmpSelInpPos[1:0] 5:4 OpAmpSelInpNeg[1:0] 3 OpAmpSelOut 2:0 RegOpAmpCfg1 Type ResVal RW 0 RW 0 RW 0 RO 0 RW '00' NI RegOpAmpCfg2 Type Bits RW 0 RW 0 RW 0 NI ResSrc ResSys ResSys ResSys ResSys ResSys OpAmp Configuration - 1 Description Enable OP Amplifier Enable/Select OpAmp as Comparator OpAmp Supply: 0-Vbat, 1-Vreg Comparator Result Selector/Enable of Comparator Interrupt Not implemented OpAmp Configuration - 2 Type Select opamp positive input source Select opamp negative input source Select opamp output pad Not implemented
Name ResAna ResAna ResAna -
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 31. BLOCKS CONSUMPTION
Following table shows the consumption of different blocks of EM6819 in typical conditions. Consumption of system, CPU, NVM access etc... have been excluded for each block to get only the consumption of the block itself. Temperature: 25C VSUP: 3V Block Brown-out Watch-dog Sleep counter wake-up RC 15 MHz RC 2 MHz RC 8 kHz Xtal BGR VLD ADC Consumption 600 nA 40 nA 90 nA 23 uA 6 uA 90 nA 400 nA 11 uA 7.2 uA 50 uA Special conditions
OpAmp
52 uA
18 uA
Timers
26 uA
SPI
16 uA
VLD source: VSUP VLD level: 0 Sampling rate: 12.5 kS/s Range: 8/8 Reference: BGR (Not included in consumption) ADC Input: PC1 = 0.618 V (Vref / 2) Comparator mode: Off OpAmp supply: VSUP Input neg: PA2 = 0V Input pos: PA3 = VSUP (3V) Output: PC1 = VSUP (3V) Comparator mode: Off OpAmp supply: VSUP Input neg: PA2 = VSUP (3V) Input pos: PA3 = 0V Output: PC1 = 0V Timer1 consumption considered CPU clock: 8kHz Prescaler1 clock: 2 MHz Prescaler2 clock: 8 kHz Timer1 clock: Prescaler1 Ck15 (2 MHz) SPI mode: Master, Auto start SCLK clock: 2 MHz (not mapped on any pad) SIN: PA4 = 0V SOUT: Not mapped on any pad Sequence: Write 0xAA ; 0x55 continously in RegSPIDOut
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 32. TYPICAL T AND V DEPENDENCIES
32.1 IDD CURRENTS
32.1.1 GENERAL CONDITIONS
Mode Active Description CPU: Software: Prescaler1: Prescaler2: Brown-out: Watch-dog: Regulator: CPU: Software: Prescaler1: Prescaler2: Brown-out: Watch-dog: Regulator: CPU: Software: Prescaler1: Prescaler2: Brown-out: Watch-dog: Regulator: CPU: Software: Prescaler1: Prescaler2: Brown-out: Watch-dog: Regulator: running at selected clock makes a loop and writes/reads continuously the RAM Running on ck_hi when available otherwise ck_lo Always running on ck_lo Enable Running on 8kHz Vreg = 1.8V enable ; multiplier enable when VSUP is low ; retention voltage off Halt state No software executed Running on ck_hi when available otherwise ck_lo Always running on ck_lo Enable Running on 8kHz Vreg = 1.8V enable ; multiplier enable when VSUP is low ; retention voltage off Halt state No software executed Disable Disable Disable Disable Vreg = 1.8V enable ; multiplier off ; retention voltage enable Halt state No software executed Disable Disable Disable Disable Vreg = 1.8V off ; multiplier off ; retention voltage off
Stand-by
Sleep
Powerdown
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Figure 31, Temperature and supply dependency for consumption @ 15 MHz
Idd 15MHz active over VSUP @ Temperature = 25C
1200
1200
Idd 15MHz active over temperature @ VSUP = 3V
1000
1000
800 Idd [uA]
Idd [uA]
800
600
600
400
400
200
200
0 2.2 2.4 2.6 2.8 VSUP [V] 3 3.2 3.4 3.6
0 -40 -20 0 20 Temperature [C] 40 60 80
Idd 15MHz std-by over VSUP @ Temperature = 25C
100 90 80 70 Idd [uA]
Idd 15MHz std-by over temperature @ VSUP = 3V
100 90 80 70 Idd [uA] 60 50 40 30 20 10 0
60 50 40 30 20 10 0 2.2 2.4 2.6 2.8 VSUP [V] 3 3.2 3.4 3.6
-40
-20
0
20 Temperature [C]
40
60
80
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Figure 32, Temperature and supply dependency for consumption @ 2 MHz
Idd 2MHz active over VSUP @ Temperature = 25C
1000 900 800 700 Idd [uA]
Idd 2MHz active over temperature @ VSUP = 3V
200 180 160 140 Idd [uA] 120 100 80 60 40 20 0
600 500 400 300 200 100 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4
-40
-20
0
20 Temperature [C]
40
60
80
Idd 2MHz std-by over VSUP @ Temperature = 25C
100 90 80 70 Idd [uA]
Idd 2MHz std-by over temperature @ VSUP = 3V
20 18 16 14 Idd [uA] 12 10 8 6 4 2 0
60 50 40 30 20 10 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4
-40
-20
0
20 Temperature [C]
40
60
80
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Figure 33, Temperature and supply dependency for consumption @ 4 MHz resonator
Idd 4MHz resonator active over VSUP @ Temperature = 25C
500 450 400 350 Idd [uA]
Idd [uA] 500 450 400 350 300 250 200 150 100 50 0
Idd 4MHz resonator active over temperature @ VSUP = 3V
300 250 200 150 100 50 0 2.2 2.4 2.6 2.8 VSUP [V] 3 3.2 3.4 3.6
-40
-20
0
20 Temperature [C]
40
60
80
Idd 4MHz resonator std-by over VSUP @ Temperature = 25C
50 45 40 35 Idd [uA]
Idd [uA] 50 45 40 35 30 25 20 15 10 5 0
Idd 4MHz resonator std-by over temperature @ VSUP = 3V
30 25 20 15 10 5 0 2.2 2.4 2.6 2.8 VSUP [V] 3 3.2 3.4 3.6
-40
-20
0
20 Temperature [C]
40
60
80
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Figure 34, Temperature and supply dependency for consumption @ 32 kHz XTAL
Idd 32kHz active over VSUP @ Temperature = 25C
20 18 16 14 Idd [uA] Idd [uA] 12 10 8 6 4 2 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4 3 2 1 0 -40 -20 0 20 Temperature [C] 40 60 80 9 8 7 6 5 4
Idd 32kHz active over temperature @ VSUP = 3V
Idd 32kHz std-by over VSUP @ Temperature = 25C
10 9 8 7 Idd [uA]
Idd [uA] 5 6
Idd 32kHz std-by over temperature @ VSUP = 3V
4
6 5 4 3 2 1 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4
3
2
1
0 -40 -20 0 20 Temperature [C] 40 60 80
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Figure 35, Temperature and supply dependency for consumption @ 8 kHz
Idd 8kHz active over VSUP @ Temperature = 25C
20 18 16 14 Idd [uA]
Idd [uA] 5 4 3 2 1 7 6
Idd 8kHz active over temperature @ VSUP = 3V
12 10 8 6 4 2 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4
0 -40 -20 0 20 Temperature [C] 40 60 80
Idd 8kHz std-by over VSUP @ Temperature = 25C
20 18 16 14 Idd [uA]
Idd [uA] 5 6
Idd 8kHz std-by over temperature @ VSUP = 3V
4
12 10 8 6 4 2 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4
3
2
1
0 -40 -20 0 20 Temperature [C] 40 60 80
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Figure 36, Temperature and supply dependency for consumption in sleep mode
Idd sleep without sleep counter wake-up over VSUP @ Temperature = 25C
5 4.5 4 3.5 Idd [uA] Idd [uA] 3 2.5 2 1.5 1 0.5 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -40 -20 0 20 Temperature [C] 40 60 80
Idd sleep without sleep counter wake-up over temperature @ VSUP = 3V
Idd sleep with sleep counter wake-up over VSUP @ Temperature = 25C
5 4.5 4 3.5 Idd [uA] Idd [uA] 3 2.5 2 1.5 1 0.5 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -40
Idd sleep with sleep counter wake-up over temperature @ VSUP = 3V
-20
0
20 Temperature [C]
40
60
80
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Figure 37, Temperature and supply dependency for consumption in power-down mode
Idd power-down over VSUP @ Temperature = 25C
700 600 500 800 Idd [nA] 400 300 200 100 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4 200 Idd [nA] 1200
Idd power-down over temperature @ VSUP = 3V
1000
600
400
0 -40 -20 0 20 Temperature [C] 40 60 80
32.2 IOL AND IOH DRIVES
Figure 38, Temperature and supply dependency for IOL & IOH on PA[7:5,3] & PC[6:5,3]
IOL on PA[7:5,3] & PC[6:5,3] over VSUP @ Temperature = 25C @ VDS = 0.3V
12 14 12 10 8 Idd [mA] Idd [mA] 8 6 4 2 2 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4 -40 -20 0 20 Temperature [C] 40 60 80
IOL on PA[7:5,3] & PC[6:5,3] over temperature @ VSUP = 3V @ VDS = 0.3V
10
6
4
0
IOH on PA[7:5,3] & PC[6:5,3] over VSUP @ Temperature = 25C @ VDS = VUSP - 0.3V
0 -2 -4 -6 Idd [mA] -8 -10 -12 -14 -16 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4
0 -2 -4 -6 -8 -10 -12 -14 -16 -40
IOH on PA[7:5,3] & PC[6:5,3] over temperature @ VSUP = 3V @ VDS = VUSP - 0.3V
Idd [mA]
-20
0
20 Temperature [C]
40
60
80
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Figure 39, Temperature and supply dependency for IOL & IOH on PA[4,2:0] & PC[7,4,2:0]
IOL on PA[4,2:0] & PC[7,4,2:0] over VSUP @ Temperature = 25C @ VDS = 0.3V
6 7 6 5 4 Idd [mA] Idd [mA] 4 3 2 1 1 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4 -40 -20 0 20 Temperature [C] 40 60 80
IOL on PA[4,2:0] & PC[7,4,2:0] over temperature @ VSUP = 3V @ VDS = 0.3V
5
3
2
0
IOH on PA[4,2:0] & PC[7,4,2:0] over VSUP @ Temperature = 25C @ VDS = VUSP - 0.3V
0 -0.5 -1 -1.5 Idd [mA]
Idd [mA] 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5
IOH on PA[4,2:0] & PC[7,4,2:0] over temperature @ VSUP = 3V @ VDS = VUSP - 0.3V
-2 -2.5 -3 -3.5 -4 -4.5 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4
-40
-20
0
20 Temperature [C]
40
60
80
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Figure 40, Temperature and supply dependency for IOL & IOH on PB[7:0]
IOL on PB[7:0] over VSUP @ Temperature = 25C @ VDS = 0.3V
12 14 12 10 8 Idd [mA] Idd [mA] 8 6 4 2 0 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4 -40 -20 0 20 Temperature [C] 40 60 80
IOL on PB[7:0] over temperature @ VSUP = 3V @ VDS = 0.3V
10
6
4
2
0
IOH on PB[7:0] over VSUP @ Temperature = 25C @ VDS = VUSP - 0.3V
0 -2 -4 -6 -8 -10 -12 -14 -16 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4 0 -2 -4 -6 -8 -10 -12 -14 -16 -40 -20
IOH on PB[7:0] over temperature @ VSUP = 3V @ VDS = VUSP - 0.3V
Idd [mA]
Idd [mA]
0
20 Temperature [C]
40
60
80
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32.3 PULL-UP AND PULL-DOWN
Figure 41, Temperature and supply dependency for pull-down & pull_up on PA[7:0] & PC[7:0]
Pull-down on PA[7:0] & PC[7:0] over VSUP @ Temperature = 25C
80000 79000 78000 77000 R [Ohm]
Pull-down on PA[7:0] & PC[7:0] over temperature @ VSUP = 3V
80000 79000 78000 77000 R [Ohm] 76000 75000 74000 73000 72000 71000 70000
76000 75000 74000 73000 72000 71000 70000 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4
-40
-20
0
20 Temperature [C]
40
60
80
Pull-up on PA[7:0] & PC[7:0] over VSUP @ Temperature = 25C
80000 79000 78000 77000 R [Ohm] R [Ohm] 76000 75000 74000 73000 72000 71000 70000 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4 80000 79000 78000 77000 76000 75000 74000 73000 72000 71000 70000 -40
Pull-up on PA[7:0] & PC[7:0] over temperature @ VSUP = 3V
-20
0
20 Temperature [C]
40
60
80
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Figure 42, Temperature and supply dependency for pull-down & pull_up on PB[7:0]
Pull-down on PB[7:0] over VSUP @ Temperature = 25C
75000 74000 73000 72000 R [Ohm] R [Ohm] 71000 70000 69000 68000 67000 66000 65000 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4 75000 74000 73000 72000 71000 70000 69000 68000 67000 66000 65000 -40 -20 0 20 Temperature [C] 40 60 80
Pull-down on PB[7:0] over temperature @ VSUP = 3V
Pull-up on PB[7:0] over VSUP @ Temperature = 25C
75000 74000 73000 72000 R [Ohm]
R [Ohm] 75000 74000 73000 72000 71000 70000 69000 68000 67000 66000 65000
Pull-up on PB[7:0] over temperature @ VSUP = 3V
71000 70000 69000 68000 67000 66000 65000 0.9 1.4 1.9 2.4 VSUP [V] 2.9 3.4
-40
-20
0
20 Temperature [C]
40
60
80
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32.4 RC OSCILLATOR 15MHZ AND 2MHZ
Figure 43, Temperature and supply dependency for internal RC oscillators
RC 15Mhz frequency error over VSUP @ Temperature = 25C
10 8 6 Frequency error [%]
RC 15Mhz frequency error over temperature @ VSUP 3V
10 8 6 Frequency error [%] 4 2 0 -2 -4 -6 -8 -10
4 2 0 -2 -4 -6 -8 -10 2.2 2.4 2.6 2.8 VSUP [V] 3 3.2 3.4 3.6
-40
-20
0
20 Temperature [C]
40
60
80
RC 2Mhz frequency error over VSUP @ Temperature = 25C
10 8 6 Frequency error [%]
RC 2Mhz frequency error over temperature @ VSUP = 3V
10 8 6 Frequency error [%] 4 2 0 -2 -4 -6 -8 -10
4 2 0 -2 -4 -6 -8 -10 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 VSUP [V]
-40
-20
0
20 Temperature [C]
40
60
80
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33.1 ABSOLUTE MAXIMUM RATINGS
Min. Max. Units Power supply VSUP-VSS - 0.2 +3.8 V Input voltage VSS - 0.2 VSUP+0.2 V Storage temperature - 40 + 125 C -2000 +2000 V Electrostatic discharge to Mil-Std-883C method 3015.7 with ref. to VSS Maximum soldering conditions As per Jedec J-STD-020C Packages are Green-Mold and Lead-free Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction
33.2 HANDLING PROCEDURES
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other CMOS integrated circuit. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range.
33.3 STANDARD OPERATING CONDITIONS
Parameter Temperature VSUP_range DCDC VSUP min IVSS max IVSUP max DCDC input current VSS CVREG (1) CVSUP (with dc-dc) LDCDC (with dc-dc) Flash data retention Flash cycling MIN -40 0.9 TYP 25 3 0.6 80 80 500 0 400 40 39 20 10k MAX 85 3.6 Unit C V V mA mA mA V nF uF uH yrs cycle Description Voltage at power-up Minimum battery voltage after start-up with DC-DC enabled; maximum current load 10 mA at 0.6V Maximum current out of VSS Pin Maximum current into VSUP Pin Maximum current from the Battery into the DCDC Reference terminal regulated voltage capacitor Supply voltage capacitor with DC-DC DC-DC coil Read and Erase state retention
1 cycle is one erase followed by 1 write Note 1: This capacitor filters switching noise from VSUP to keep it away from the internal logic and memory cells. In noisy systems the capacitor should be chosen higher than minimum value.
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33.4 TYPICAL 32KHZ CRYSTAL SPECIFICATION
Fq 32768 Hz nominal frequency Rqs 35 KOhm typical quartz serial resistance CL 8.2 pF typical quartz load capacitance df/f ppm quartz frequency tolerance 30 Watch type crystal oscillator (i.e Microcrystal DS15 ), connected between QIN and Qout terminal.
33.5 TYPICAL 4MHZ CRYSTAL SPECIFICATION
FR RS CS CP LS df/f 4 22 3.8 19.8 460 30 MHz Ohm pF pF uH ppm nominal frequency Typical equivalent resistor Typical equivalent serial capacitor Typical equivalent parallel capacitor Typical equivalent inductor quartz frequency tolerance
33.6 TYPICAL 4MHZ RESONATOR SPECIFICATION
FR 4 MHz nominal frequency RS 9 Ohm Typical equivalent resistor CS 0.007 pF Typical equivalent serial capacitor CP 2.39 pF Typical equivalent parallel capacitor LS 210 mH Typical equivalent inductor df/f % Resonator frequency tolerance 0.5 Watch type resonator oscillator CERALOCK Murata CSTLS4M00G53-B0, connected between QIN and Qout terminal.
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33.7 DC CHARACTERISTICS - POWER SUPPLY CURRENTS
Conditions: In active mode, the software makes a loop and writes/reads continuously the RAM, the following blocks are active: NVM instructions read access Regulator RAM read/write access Voltage multiplier in low voltage mode Prescalers 1 & 2 Brown-out Selected oscillator Power on reset RC 8kHz Internal bias current generation In stand-by mode, the software execution is stopped; the following blocks are active: Prescalers 1 & 2 Voltage multiplier in low voltage mode Selected oscillator Brown-out RC 8kHz Power on reset Regulator Internal bias current generation In sleep mode, the software execution is stopped; the following blocks are active: RC 8kHz Brown-out Regulator Power on reset Voltage multiplier in low voltage mode Internal bias current generation In power-down mode, the software execution is stopped; the following blocks are active: Power on reset Internal bias current generation Following table includes product: EM6819FX-AXX0 / -BXX0 / -BXX4 , all measures without DCDC Parameter Conditions Symbol Min. Typ. Max. Unit ACTIVE Supply Current VSUP =3V, -40 to 85C, 7.5 MIPS IVSUPA15MD1 1.05 1.7 mA
CPU on RC=15MHz, no div CPU on RC=2MHz, no div
ACTIVE Supply Current ACTIVE Supply Current
CPU on XTal=32KHz, no div
VSUP =3V, -40 to 85C, 1 MIPS VSUP =1.2V, -40 to 85C, 1MIPS Note2 VSUP =3V, -40 to 85C, 16 kIPS VSUP =3V, -40 to 60C, 16 kIPS VSUP =3V, -40 to 85C, 4 kIPS VSUP =3V, -40 to 85C, HF Div=1 VSUP =3V, -40 to 85C, HF Div=1 StdByFastWkUp=0 VSUP =1.2V, -40 to 85C, HF Div=1 VSUP =3V, -40 to 85C, HF RC off StdByFastWkUp=0 VSUP =1.2V, -40 to 85C, HF RC off StdByFastWkUp=0, Note2 VSUP =3V, -40 to 60C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 85C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 60C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 85C StdByFastWkUp=0 VSUP =3V, -40 to 60C, RC 8kHz on StdByFastWkUp=0 VSUP =3V, -40 to 85C, RC8kHz off StdByFastWkUp=0 VSUP =3V, -40 to 25C VSUP =3V, -40 to 60C VSUP =3V, -40 to 85C
IVSUPA2MD1 IVSUPA2MD1 IVSUPA32K IVSUPA32K IVSUPA8K IVSUPH15MD1 IVSUPH2MD1 IVSUPH2MD1 IVSUPH32K IVSUPH32K IVSUPH32K IVSUPH8K IVSUPH8K IVSUPSWK IVSUPSWK IVSUPSLEEP IVSUPPWDWN IVSUPPWDWN IVSUPPWDWN
140 490 4.2 4.2 3.5 72 14 35 2.3 5 2.3 2.3 2.3 1.95 1.95 1.9 0.45 0.45 0.45
250 13 8
uA uA uA uA uA uA uA uA
ACTIVE Supply Current
CPU on RC=8KHz, no div
Std-by Supply Current
Peri on RC=15MHz, no div
Std-by Supply Current
Peri on RC=2MHz, no div
Std-by Supply Current
Peri on RC=2MHz (2), no div
10
uA uA
Std-by Supply Current
Peri on XTal=32KHz, no div
5 9 5 8 4
uA uA uA uA uA uA
Std-by Supply Current
Peri on RC=8KHz, no div
Sleep Supply Current
Wake-up counter on
Sleep Supply Current
Wake-up counter off
Powerdown
0.65 0.8 1.65
uA uA uA
Note 2: Internal voltage multiplier enable.
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Following table includes product: EM6819FX-XX5 / -XX6, all measures without DCDC Parameter Conditions Symbol Min. Typ. ACTIVE Supply Current VSUP =3V, -40 to 85C, 7.5 MIPS I 0.85
CPU on RC=15MHz, no div CPU on RC=2MHz, no div
VSUPA15MD1
Max. 1.2 180 13 8
Unit mA uA uA uA uA uA uA uA
ACTIVE Supply Current ACTIVE Supply Current
CPU on XTal=32KHz, no div
VSUP =3V, -40 to 85C, 1 MIPS VSUP =1.2V, -40 to 85C, 1MIPS Note2 VSUP =3V, -40 to 85C, 16 kIPS VSUP =3V, -40 to 60C, 16 kIPS VSUP =3V, -40 to 85C, 4 kIPS VSUP =3V, -40 to 85C, HF Div=1 VSUP =3V, -40 to 85C, HF Div=1 VSUP =3V, -40 to 85C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 60C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 85C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 60C, HF RC off StdByFastWkUp=0 VSUP =3V, -40 to 85C StdByFastWkUp=0 VSUP =3V, -40 to 60C, RC 8kHz on StdByFastWkUp=0 VSUP =3V, -40 to 85C, RC8kHz off VSUP =3V, -40 to 25C
IVSUPA2MD1 IVSUPA2MD1 IVSUPA32K IVSUPA32K IVSUPA8K IVSUPH15MD1 IVSUPH2MD1 IVSUPH32K IVSUPH32K IVSUPH8K IVSUPH8K IVSUPSWK IVSUPSWK IVSUPSLEEP IVSUPPWDWN IVSUPPWDWN IVSUPPWDWN
116 490 4.2 4.2 3.5 72 14 2.3 2.3 2.3 2.3 1.95 1.95 1.9 0.45 0.45 0.45
ACTIVE Supply Current
CPU on RC=8KHz, no div
Std-by Supply Current
Peri on RC=15MHz, no div
Std-by Supply Current
Peri on RC=2MHz, no div
Std-by Supply Current
Peri on XTal=32KHz, no div
10 5 9 5 8 4
uA uA uA uA uA uA uA
Std-by Supply Current
Peri on RC=8KHz, no div
Sleep Supply Current
Wake-up counter on
Sleep Supply Current
Wake-up counter off
Powerdown Current
VSUP =3V, -40 to 60C VSUP =3V, -40 to 85C
0.65 0.8 1.65
uA uA uA
Note 2: Internal voltage multiplier enable.
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33.8 DC CHARACTERISTICS - VOLTAGE DETECTION LEVELS
Parameter Conditions POR VSUP static level on rising -40 to 85C edge POR VSUP static level on falling -40 to 85C edge -40 to 25C Temperature coefficient 25 to 85C VLD0, VBAT decreasing 25C VLD1, VBAT decreasing 25C VLD2, VBAT decreasing 25C VLD3, VBAT decreasing 25C VLD4, VBAT decreasing 25C VLD5, VBAT decreasing 25C VLD6, VBAT decreasing 25C VLD7, VBAT decreasing 25C VLD8, VBAT decreasing 25C VLD9, VBAT decreasing 25C VLD10, VBAT decreasing 25C VLD11, VBAT decreasing 25C VLD12, VBAT decreasing 25C VLD13, VBAT decreasing 25C VLD14, VBAT decreasing 25C VLD15, VBAT decreasing 25C VLD16, VBAT decreasing 25C VLD17, VBAT decreasing 25C VLD18, VBAT decreasing 25C VLD19, VBAT decreasing 25C VLD20, VBAT decreasing 25C VLD21, VBAT decreasing 25C VLD22, VBAT decreasing 25C VLD23, VBAT decreasing 25C VLD24, VBAT decreasing 25C VLD25, VBAT decreasing 25C VLD26, VBAT decreasing 25C VLD27, VBAT decreasing 25C VLD28, VBAT decreasing 25C VLD29, VBAT decreasing 25C VLD30, VBAT decreasing 25C VLD31, VBAT decreasing 25C VLD trim bit step / LSB Symbol VPORRIS VPORFAL TVLD_COEF_LO TVLD_COEF_HI VVLD0 VVLD1 VVLD2 VVLD3 VVLD4 VVLD5 VVLD6 VVLD7 VVLD8 VVLD9 VVLD10 VVLD11 VVLD12 VVLD13 VVLD14 VVLD15 VVLD16 VVLD17 VVLD18 VVLD19 VVLD20 VVLD21 VVLD22 VVLD23 VVLD24 VVLD25 VVLD26 VVLD27 VVLD28 VVLD29 VVLD30 VVLD31 -0.110 -0.117 Min. Typ. 0.7 0.58 0.01 0.01 0.800 0.820 0.840 0.860 0.880 0.900 0.920 0.940 0.960 0.980 1.000 1.100 1.150 1.200 1.300 1.400 1.450 1.500 1.600 1.700 1.900 2.100 2.300 2.400 2.500 2.550 2.600 2.700 2.800 2.900 2.950 3.000 1.7 Max. 0.86 0.74 0.134 0.142 Unit V V %/C %/C V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V mV/V
2.981
3.025
33.9 DC CHARACTERISTICS - REFERENCE VOLTAGE
Parameter Temperature coefficient Temperature coefficient Reference voltage after trimming Output load current on PA[2] Conditions -40 to 25C 25 to 85C
VSUP =3V, 25C VSUP =3V, -40 to 85C, VBGP output
Symbol TBGR_COEF_LO TBGR_COEF_HI VBGP
Min. Typ. Max. -0.102 0.01 0.128 -0.112 0.01 0.136 1.225 1.236 1.247 10
Unit %/C %/C V uA
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33.10 DC CHARACTERISTICS - DC-DC CONVERTER
VBAT is input voltage of DC-DC (main Battery), VSUP is output voltage of DC-DC Parameter Conditions Symbol Min. -40 to 85C Battery voltage range VBAT 0.9 -40 to 85C ; DC-DC level 2.1 VDCDC2.1 DC-DC level 2.5 DC-DC level 2.9 DC-DC level 3.3 Output ripple Max external current current load DC-DC efficiency
VBATMIN to VBATMAX -40 to 85C ; VBATMIN to VBATMAX -40 to 85C ; VBATMIN to VBATMAX -40 to 85C ; VBATMIN to VBATMAX -40 to 85C ; VBATMIN to VBATMAX -40 to 85C ; @VBATMIN @ VBATMax, VDCDC =3.3V -40 to 85C ; VBATMIN to VBATMAX
Typ. 2.1 2.5 2.9 3.3
Max. 1.8
Unit V V V V V
VDCDC2.5 VDCDC2.9 VDCDC3.3 VRIP ILOAD09V ILOAD18V DCDCEFF
+/-100 40 150 85
mV mA mA %
33.11 DC CHARACTERISTICS - OSCILLATORS
Parameter 32KHz XTAL Integrated Input capacitor 32KHz Xtal Integrated Output capacitor Conditions Reference on VSS
T=25C
Symbol CIN COUT tdosc tdosc tdosc
Min.
Typ. 7 14 0.5 1 3 0.04 0.004
Max.
Unit pF pF
Reference on VSS T=25C 32KHz Xtal Oscillator start VSUP > VSUPMin time T=25C 4MHz resonator start time VSUP > VSUPMin T=25C 4MHz XTal start time VSUP > VSUPMin T=25C RC oscillator 15MHz -40 to 25C Temperature coefficient RC oscillator 15MHz 25 to 85C Temperature coefficient RC Oscillator 15MHz After trimming, 25C RC Oscillator 15MHz Trimm range 15MHz RC Oscillator 15MHz Trimm step / LSB RC oscillator 2MHz -40 to 25C Temperature coefficient RC oscillator 2MHz 25 to 85C Temperature coefficient RC Oscillator 2MHz After trimming, 25C RC oscillator 2MHz Trimm range 2MHz RC oscillator 2MHz Trimm step / LSB RC Oscillator 8kHz
4 10 30 0.106 0.069
s ms ms %/C %/C MHz % kHz
TRC15_COEF_LO -0.018 TRC15_COEF_HI FRC15M -0.055
14.6129
14.7456 14.8783 +50/-30
47.8 TRC2_COEF_LO TRC2_COEF_HI FRC1MHz -0.031 -0.058 1.976 0.08 0.05 2
+50/-30
0.177 0.164 2.024
%/C %/C MHz % kHz kHz
8.3 6.7
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33.12 DC CHARACTERISTICS - VHIGH
Parameter VHIGH level VSUP low VHIGH level VSUP high Conditions
VSUP < 1.6V, -40 to 85C VSUP > 1.6V, -40 to 85C
Symbol VHighLOW VHighHI
Min. 1.6 VSUP0.1
Typ.
Max. 2.0 VSUP
Unit V V
33.13 DC CHARACTERISTICS - OPAMP
Parameter Open loop gain Gain band width Phase margin PSRR @ 100kHz CMRR @ 100kHz Noise Input offset Reaction time to enable signal Output voltage swing Current load IOH Current load IOL Slew rate Conditions
VSUP =3V, -40 to 85C VSUP =3V, -40 to 85C VSUP =3V, -40 to 85C VSUP =3V, -40 to 85C VSUP =3V, -40 to 85C VSUP =3V, -40 to 85C VSUP =3V, -40 to 85C VSUP =3V, -40 to 85C VSUP =3.0V, -40 to 85C VINCM=350mV OPAMP supply Vreg VSUP =3V, -40 to 85C VSUP =3V, -40 to 85C VSUP =3.0V, -40 to 85C VINCM=350mV
Symbol A0 GBW PM PSRR CMRR NOISE VINOFFSET TON VOS ILOAD ILOAD SR
Min.
-50
Typ. 70 0.7 60 -24 -47 10 0 20 1.85
Max.
50
Unit dB MHz dB dB uV mV us V uA uA V/us
1.3 -180
150 0.6
33.14 DC CHARACTERISTICS - ADC
10 bits ADC considered (RegADCOut1.ADCOutLSB is ignored) Parameter Conditions Symbol ADC offset -40 to 25C TADC_COEF_LO Temperature coefficient ADC offset 25 to 85C TADC_COEF_HI Temperature coefficient VSUP =3V, 25C ADC offset ADC ADC DNL ADC INL + gain error ADC INL best fit ADC DNL range 8/8 ADC DNL range 6/8 ADC DNL range 4/8 ADC INL best fit range 6/8 ADC INL best fit range 4/8 ADC INL best fit range 3/8
ADCref = VBGP ; Rate 91kS/s Range 8/8 VSUP =3V, -40 to 85C ADCref = VBGP ; Rate 91kS/s ; Range 8/8 VSUP =3V, -40 to 85C ADCref = VBGP ; Rate 91kS/s ; Range 8/8 VSUP =3V, -40 to 85C ADCref = VBGP ; Rate 91kS/s ; Range 8/8 VSUP =3V, -40 to 85C ADCref = VBGP ; Rate 45kS/s ; Range 8/8 VSUP =3V, -40 to 85C ADCref = VBGP ; Rate 45kS/s ; Range 6/8 VSUP =3V, -40 to 85C ADCref = VBGP ; Rate 45kS/s ; Range 4/8 VSUP =3V, -40 to 85C ADCref = VBGP ; Rate 45kS/s ; Range 6/8 VSUP =3V, -40 to 85C ADCref = VBGP ; Rate 45kS/s ; Range 4/8 VSUP =3V, -40 to 85C ADCref = VBGP ; Rate 45kS/s ; Range 3/8
Offset
Min. -0.108 -0.114 -4 -2 -13 -6
Typ. 0.01 0.02 0 0 0 0 +/0.5 +/0.5 +/0.5 +/- 4 +/- 4 +/- 4
Max. 0.135 0.150 4 2 13 6
Unit %/C %/C LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB
ADCDNL ADCINLT ADCINLbestfit ADCDNL6/8 ADCDNL6/8 ADCDNL4/8 ADCINLT6/8 ADCINLT4/8 ADCINLT4/8
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33.15 DC CHARACTERISTICS - TEMPERATURE SENSOR
10 bits ADC considered (RegADCOut1.ADCOutLSB is ignored) Parameter Conditions Symbol Min. Typ. Max. Unit VSUP =3V Temp sensor result at 25 Tempsens25 416 LSB Temp sensor result at -40 VSUP =3V Tempsens-40 183 LSB VSUP =3V Temp sensor result at 60 Tempsens60 550 LSB VSUP =3V Temp sensor result at 85 Tempsens85 639 LSB VSUP =3V ; Temp range 0 - 60 Temp sensor slope Tempsensslope 3.8 LSB/ VSUP =3V ; Temp range 0 - 60 Temp sensor linearity Tempsenslin +/-0.8 % Note: offset & calibration values stored in NVM are coded on 11bits than values are twice values in above table.
33.16 DC CHARACTERISTICS - I/O PINS
Conditions: T= -40 to 85C, VSUP=3.0V (unless otherwise specified) Parameter Conditions Symbol Input Low voltage Ports A,B, C VIL Input High voltage Ports A,B, C Input Hysteresis PA[7:0], PB[7:0], PC[7:0] IOL (high current drives) PA[7:5,3], PB[7:0], PC[6:5,3] Temp=25C Min. VSS Typ. Max. 0.2* VSUP VSUP 0.42 4.2 9.9 19.8 33.0 5.2 10.4 17.3 -12.7 -25.4 -42.3 -3.3 -6.6 -11.0 70k 70k 20k Unit V
VIH VHyst IOL IOL IOL IOL IOL IOL IOH IOH IOH IOH IOH IOH RPD RPU RPDTM
0.8* VSUP
V V mA mA mA mA mA mA mA mA mA mA mA mA Ohm Ohm Ohm
VSUP =3.0V , VOL=0.3V VSUP =3.0V , VOL=0.6V VSUP =3.0V , VOL=1.0V VSUP =3.0V , VOL=0.3V IOL VSUP =3.0V , VOL=0.6V PA[4,2:0], PC[7,4,2:0] VSUP =3.0V , VOL=1.0V IOH (high current drives) VSUP =3.0V , VOH= VSUP - 0.3V PA[7:5,3], PB[7:0], VSUP =3.0V , VOH= VSUP - 0.6V PC[6:5,3] VSUP =3.0V , VOH= VSUP - 1.0V VSUP =3.0V , VOH= VSUP - 0.3V IOH VSUP =3.0V , VOH= VSUP - 0.6V PA[4,2:0], PC[7,4,2:0] VSUP =3.0V , VOH= VSUP - 1.0V Input Pull-down VSUP =3.0V, Pin at 3.0V Port A,B,C Input Pull-up Port A,B,C VSUP =3.0V, Pin at 0.0V Input Pull-down VSUP =3.0V, Pin at 3.0V TM
1.6
-6.5
-1.0
35k 35k
100k 100k
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 34. PACKAGE DRAWINGS
34.1 DIMENSIONS OF TSSOP28 PACKAGE
S Y M B
3
2
1
B
C
O
B
E E1
C L
A A1 A2 b b1 c D E1
L
DIMENSIONS in MILLIMETERS MIN. NOM. MAX.
0.05 0.85 0.19 0.19 0.09 4.30 0.50 0.90 0.22 9.70 BSC 4.40 0.65 BSC 6.40 BSC 0.60 1.10 0.15 0.95 0.30 0.25 0.20 4.50 0.70
e
E L
N
C O C
0
8
TOP VIEW
SEE DETAIL "A"
END VIEW
(14)
b
A2
A
0.25
e D
A1
SEATING PLANE
(O )C
(1.00)
C
L
(VIEW ROTATED 90 C.W.)
DETAIL 'A'
(14)
TSSOP28
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x
34.2 DIMENSIONS OF TSSOP24 PACKAGE
S Y M B
3
2
1
B
C
O
B
E E1
C L
A A1 A2 b b1 c D E1
L
DIMENSIONS in MILLIMETERS MIN. NOM. MAX.
0.05 0.85 0.19 0.19 0.09 4.30 0.50 0.90 0.22 7.80 BSC 4.40 0.65 BSC 6.40 BSC 0.60 1.10 0.15 0.95 0.30 0.25 0.20 4.50 0.70
e
E L
N
C O C
0
8
TOP VIEW
SEE DETAIL "A"
END VIEW
(14)
b
A2
A
0.25
e D
A1
SEATING PLANE
(O )C
(1.00)
C
L
(VIEW ROTATED 90 C.W.)
DETAIL 'A'
(14)
TSSOP24 (0.65mm pitch, 4.4mm body width)
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x
34.3 DIMENSIONS OF TSSOP20 PACKAGE
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x
34.4 DIMENSIONS OF TSSOP16 PACKAGE
S Y M B
3
2
1
B
C
O
B
E E1
C L
A A1 A2 b b1 c D E1
L
DIMENSIONS in MILLIMETERS MIN. NOM. MAX.
0.05 0.85 0.19 0.19 0.09 4.30 0.50 0.90 0.22 5.00 BSC 4.40 0.65 BSC 6.40 BSC 0.60 1.10 0.15 0.95 0.30 0.25 0.20 4.50 0.70
e
E L
N
C O C
0
8
TOP VIEW
SEE DETAIL "A"
END VIEW
(14)
b
A2
A
0.25
e D
A1
SEATING PLANE
(O )C
(1.00)
C
L
(VIEW ROTATED 90 C.W.)
DETAIL 'A'
(14)
TSSOP16 (0.65mm pitch, 4.4mm body width)
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x
34.5 DIMENSIONS OF SO8 PACKAGE
3
2
1
SO8 - 150
H
PARTING LINE
THIS TABLE IN MILLIMETERS
S Y M B O L
N
C O C
L
DETAIL A
TOP VIEW
e
B A2
SEATING PLANE SEE DETAIL A
A A1 A2 B C D E e H 5.84 L 0.41 N C 0 O C
COMMON DIMENSIONS MAX. NOM. MIN. 1.63 1.55 1.73 0.15 0.127 0.25 1.47 1.55 1.40 0.41 0.35 0.49 0.19 0.25 0.20 4.80 4.93 4.98 3.94 3.81 3.99
1.27 BSC
5.99 0.64 5
8
6.20 0.89 8
C
A D
SIDE VIEW
A1
E
END VIEW
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x
34.6 DIMENSIONS OF QFN32 PACKAGE
Copyright (c) 2010, EM Microelectronic-Marin SA 6819-DS, Version 3.0 ,8-Jul-10
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x
34.7 DIMENSIONS OF QFN20 PACKAGE
D MIN. e
PIN #1 ID
NOM. 0.50 0.50 0.25 2.60 2.60 0.85 0.02 0.20 0.20min 4.0 4.0 0.15max
MAX. 0.55 0.30 2.70 2.70 0.90 0.05
E
L b D2 E2 A A1 A3
0.45 0.18 2.50 2.50 0.80 0.00
TOP VIEW
A A1 A3
SIDE VIEW
K D E D2 D2/2 K L E2/2
SEE DETAIL "A"
L1
ALL DIMENSIONS ARE IN MILLIMETERS
4*e
2 1
E2 K b e 4*e
BOTTOM VIEW
SEE DETAIL "A
TERMINAL/SIDE
L e
TERMINAL TIP
L1
PIN #1 ID
DETAIL "A"
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 35. PACKAGE MARKING
The first line of the package marking contains the Revision ID and the bonding option The remaining lines contain Lot identification information First Line: EM6819 XY wheras XY= Circuit hardware information and package pinout
Current Package markings EM6819 EA (hardware E with DCDC available) EM6819 EB (hardware E without DCDC) For changes refer to the Errata section.
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 36. ERRATA
EM6819FX-A00X, EM6819Fx-A10x package marking `EM6819 DA' EM6819Fx-B00x, EM6819Fx-B10x package marking `EM6819 DB' - unstable IVDD consumption possible in powerdown mode - External reference input for ADC limited to 2.8V Current Revision EM6819FX-A00X, EM6819Fx-A10x package marking `EM6819 EA' EM6819Fx-B00x, EM6819Fx-B10x package marking `EM6819 EB' - External reference input for ADC limited to 2.8V
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EM6819FX-A00X, EM6819Fx-A10x www..com EM6819Fx-B00x, EM6819Fx-B10x 37. ORDERING INFORMATION
The full ordering information is composed out of the - Part number - The package type and pin count for given part number (to be found in table EM6819 family on page 11) - The delivery form (Stick, Tape, Tray) depending on the selected package Examples: - EM6819F6-B100-TP028BD - EM6819F4-A000-LF020D Part Number Refer to table EM6819 family on page 11 for the different part numbers I.e EM6819F6-A000 Package Type and package pin count Refer to table EM6819 family on page 11 for available packages for a given part number. Packages: QFN, TSSOP, SO Pincounts: 8, 16, 20, 28, 32 Package and pincount codes: QFN: LF032 LF020 TSSOP: TP028 TP020 TP016 SO008
SO:
Delivery Form The delivery form depends on the selected package type For TSSOP, SO packages - BD Tape and Real For QFN packages -D Tray Die/wafer form delivery Delivery in die or wafer form is also possible. Please contact EM Microelectronic directly if such delivery is requested.
EM Microelectronic-Marin SA (EM) makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in EM's General Terms of Sale located on the Company's web site. EM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of EM are granted in connection with the sale of EM products, expressly or by implications. EM's products are not authorized for use as components in life support devices or systems.
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